Hi,
I was having the same problem, but I figured it out. Shut everything down,
then turn on the SDR first and the computer second. Next type sudo
/usr/local/bin/niusrprio_pcie *stop*. Do not type start before using the
stop command. If you type start then later type stop, it still won't work.
I'm
The phase noise comes from the B210 LO (RF synthesizer), and is present
regardess of the frequency offset...you are misled by the log axis of the plot.
The close-in noise can be improved by using a high quality external 10 MHz
source. The control loop action of the synthesizer translates the re
> Any ideas why? Thank you.
This might just be the limited precision of fixed point math used on the FPGA.
Cheers,
Sylvain
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