On 04/15/2019 09:48 PM, Town Black wrote:
Hi Marcus,
Thank you for your reply, your advice will be very helpful for me, but
I have another question.We have made the 2 tx timed-aligned
automatically by using multi_usrp object, so how can we make the 1rx
and 2 tx timed-aligned automatically nex
On 04/15/2019 05:34 AM, Town Black via USRP-users wrote:
Hi friend，
I am a user of ettus e310 ,and I have installed uhd 3.9.2. In the
e310, there are 2 rx and 2 tx. I want to build a MISO system, where 2
tx sends signals, 1 rx receives signals at the same time, I only have
one e310, will it b
Hello,
I am trying to build basic OOT module for N310. My UHD version is
3.14.0.0-rc1 (I also tried with 3.14.0.0). I can build FPGA image
without OOT modules for N310. But when i try building with OOT module
using this command, it gives this error:
rcetin@rcetin-ThinkPad-W530:~/rfnoc/fpga/
Hallo guys,
I have a question relating the RFNoC sandbox. We developed our FPGA-images
on UHD 3.14.0-rc1 and would like to update now to the final release of UHD
3.14. Is this possible with pybombs and when yes, how? We couldn't find
much of information about it.
Or how would you otherwise upgrad
Hi friend，
I am a user of ettus e310 ,and I have installed uhd 3.9.2. In the e310,
there are 2 rx and 2 tx. I want to build a MISO system, where 2 tx sends
signals, 1 rx receives signals at the same time, I only have one e310, will
it be possible to make the three parts work synchronously?
Best re
