[USRP-users] RFNoC Replay block example

2018-10-31 Thread Rob Kossler via USRP-users
There are a couple of issues with the replay block example: - It doesn't work correctly for ports other than the default port because some function calls have missing "port" args or they are set to zero rather than using the specified port (see attached patch file with changes). - It can take a ver

Re: [USRP-users] RFNoC block fpga control source issues

2018-10-31 Thread Samuel Prager via USRP-users
Hi Jonathon, Yes I don’t really see how this what about the fifo flop vs fifo would be causing the issue either so it would make sense if there is something more complex going on... I am using chdr framer to generate my command packet headers, which is where it was causing problems. I haven’t

Re: [USRP-users] RFNoC Replay block for E310?

2018-10-31 Thread Jason Matusiak via USRP-users
I might be speaking out of turn here since I don't really know what the replay block does. But in the past, I successfully created a block that used a .coe file as a generated signal I transmitted over and over again. It was a pretty easy OOT module that just used a Xilinx core if I remember r

Re: [USRP-users] Saturation issue with low amplitude (USRP N310)

2018-10-31 Thread Lundberg, Daniel via USRP-users
I appreciate the responsiveness. I am fairly new to the N310 and the RFNOC blocks, so I would not entirely rule out the possibility of user error at this point. If there are additional diagnostics I could supply, please let me know. -Dan From: Michael West Sent: Tuesday, October 30, 2018 8:00

Re: [USRP-users] RFNoC block fpga control source issues

2018-10-31 Thread Jon Pendlum via USRP-users
Hi Sam, Interesting find. Fundamentally, chdr_frame was designed to buffer and release on packet boundaries. This is due to the crossbar being packet switched and ensures packets flow through the crossbar at full rate. Generally, that is only important for sample data, which could have large packe