Hello. I'm having an error after installing the software-office. Tell me
how can I fix this error ??
root@ettus-e3xx-sg3:~/newinstall/usr/lib/uhd/examples# ./rx_samples_to_file
--freq 100e6 --gain 0 --ant TX/RX --rate 1e6 --null
Creating the usrp device with: ...
[INFO] [UHDlinux; GNU C++ version
It seems that this issue has tripped up several people. It might be
prudent to not push the FPGA changes to master until you have the
corresponding UHD updates ready to go.
On Thu, Aug 30, 2018 at 12:49 PM Brent Stapleton
wrote:
> Hi Juan,
>
> In general, FPGA images built from the submodule in
I used rfnocmodtool from UHD3.13 to generate a new noc block. The id it
assigned the block had a leading 0. Unfortunately, the tool appears to have
dropped the leading 0 in the auto-generated xml file, which led to grc and
uhd_usrp_probe not being able to find the controller and name for the block.
As a note, these mismatches can occur if you use pybombs to manage your
install and do pybombs update uhd-fpga. If you're a pybombs user, my
recommendation is to ignore the uhd-fpga directory altogether, and from
within uhd/fpga run git submodule init, followed by git pull.
Brent, is this somethin
Hello Arun,
The gpio example is the first place to look for a reference.
https://github.com/EttusResearch/uhd/blob/master/host/examples/gpio.cpp
A description of the GPIO header on the B20xmini can be found here
http://files.ettus.com/manual/page_usrp_b200.html#b200_hw_ref_ext
Regards,
Derek
On
Hi Arun,
in the uhd/host/examples directory, you'll find gpio.cpp !
Note that you'll need to bitbang SPI that way from the host; that can
work, but it's going to be slow.
Alternatively, if you are familiar with FPGA development, implementing
another SPI host in the FPGA should be thoroughly
Hi
We brought B205mini recently and we want to use three GPIO to control some
external device which require SPI interface, in the schematics the header
mentioned is J5 for GPIO while website USRP Hardware Driver and USRP Manual:
USRP B2x0 Series is mentioning J6 as GPIO header. Can you please su
Hi Jose,
In general, FPGA images built from the submodule in the uhd repository will
be compatible with UHD built from that commit. The HEADs of the two master
branches (uhd and fpga) do not have that guarantee. For example, the HEAD
of uhd master branch (as I write this email) is the git commit 3
Hi Juan,
In general, FPGA images built from the submodule in the uhd repository will
be compatible with UHD built from that commit. The HEADs of the two master
branches (uhd and fpga) do not have that guarantee. For example, the HEAD
of uhd master branch (as I write this email) is the git commit 3
On 08/30/2018 12:59 AM, Bob Conley via USRP-users wrote:
While following the procedure outlined in AN315 "Software Development
on the E3xx USRP - Building RFNoC UHD / GNU Radio / gr-ettus from
Source" I get the following error during make in the "Building
rfnoc-devel UHD" procedure:
Tail of
Hello,
I created an image for the N310 with the fpga master branch commit
615d9b8eeb94ee2d19c3b1e7aa526d4999495e05.
I have UHD installed master branch commit
3b42e6f029f0d3de0f54d720964357aa0a32986f. When I go to probe the N310 I get the
following error
[ERROR] [0/DmaFIFO_0] Major compat n
Michael and Sylvain, thank you very much for your answers!
I will start hacking right now!.
Have a nice day!
El jue., 30 ago. 2018 a las 15:42, Sylvain Munaut (<246...@gmail.com>)
escribió:
> Yeah the FPGA and even the FX3 are fully loaded from the host. There is
> nothing permanent written on
Yeah the FPGA and even the FX3 are fully loaded from the host. There is
nothing permanent written on the B2xx devices, so worst case you unplug /
replug and it will reprogram everything starting from the FX3 ROM loader
which you can't possible overwrite.
As for FPGA mods, as long as you don't chan
I'm pretty sure you can't break the loader by changing the FPGA image. The
cypress IC handles the loading. I've played around with the FPGA image a
lot, including some broken images, and never had a problem loading a new
image.
On Mon, Aug 27, 2018 at 4:38 PM Javier Coronel (Expo Impex, S.L.) vi
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