While following the procedure outlined in AN315 "Software Development on
the E3xx USRP - Building RFNoC UHD / GNU Radio / gr-ettus from Source" I
get the following error during make in the "Building rfnoc-devel UHD"
procedure:
Tail of console output
-
[ 75%] Build
There appears to be a compatibility mismatch for the latest FPGA master and
UHD. I built a new image from fpga master today, but uhd_usrp_probe from
UHD (w/ -DENABLE_RFNOC=ON) gives me the error message below:
[INFO] [0/DmaFIFO_0] Initializing block control (NOC ID: 0xF1F0D000)
[ERROR] [0
Hi Rob,
I'm assuming you were able to work through the issue because you were on
the right track, but I wanted to make sure you got a response. The
solution is to create a .yml file containing the blocks and parameters
desired for the RFNoC image and use that as an input to
uhd_image_builder.py.
On 08/29/2018 03:38 PM, Malik Saad via USRP-users wrote:
I have edited python block in gnuradio "Embeded Python Block"
Folloing is the part of code.
def __init__(self, Id='', default_value=2.37e9, start=1.9e9
,stop=1.9e9, step=2e6): # only default arguments here
gr.sync_block.__init
I have edited python block in gnuradio "Embeded Python Block"
Folloing is the part of code.
def __init__(self, Id='', default_value=2.37e9, start=1.9e9 ,stop=1.9e9,
step=2e6): # only default arguments here
gr.sync_block.__init__(
self,
name='Frequency sweeper',
There is a bug in the DMA FIFO read logic that is likely the root cause of
this. Changing the line below in axi_dma_fifo.v fixed it for me.
OUTPUT2: begin
// Replicated write logic to break a read timing critical path for
read_count
read_count <= (output_page_boundry < occupied_minus_one) ?
outpu
Works like a charm. Thanks!
-Andrew
On Wed, Aug 29, 2018 at 5:34 AM, Jason Matusiak <
ja...@gardettoengineering.com> wrote:
> Andrew,
>
> I have this issue all the time. To get around it, I go into properties of
> the block (double click on it in the GRC), go to the the RFNoC Config tab,
> and
Thanks Brian, that certainly sounds like the problem I’m experiencing. I’ll
try rebuilding my FPGA and UHD as you suggest. If that doesn’t work or I get
more information, I let you know.
Thanks again,
Al
From: Brian Padalino
Sent: Tuesday, August 28, 2018 8:57 PM
To: Alan Conrad
Cc: USRP-u
Andrew,
I have this issue all the time. To get around it, I go into properties of the
block (double click on it in the GRC), go to the the RFNoC Config tab, and
change the Device Select to 0 for one of them, and 1 for the other. There is
some sort of issue (I don't recall why, but it was exp
