Re: [USRP-users] Ethernet over SFP+ in custom FPGA design (X3x0)

Hey Sugandha, thanks for your help. I apologize for the incredible delay from my side, but back to my question. We want to port a hole IP solution from some proprietary hardware to the USRP and evaluate the costs (mainly development time) of migrating our IP to RFNoC vs. a custom image. The crux

Re: [USRP-users] Fwd: USRP2 schematic vs. FPGA source discrepancy

Hi Robin, Thank you for the information. I experimented a bit and it turned out that the V15 pin is indeed connected to SW1, so the schematic was more informative here. The USRP2 FPGA source code has the pin declared, but it is not used at all