Yes, they share L2 and L1i.
Brice
Le 30/08/2017 02:16, Gilles Gouaillardet a écrit :
> Prentice,
>
> could you please run
> lstopo --of=xml
> and post the output ?
>
> a simple workaround could be to bind each task to two consecutive cores
> (assuming two consecutive cores share the same FPU, w
Prentice,
could you please run
lstopo --of=xml
and post the output ?
a simple workaround could be to bind each task to two consecutive cores
(assuming two consecutive cores share the same FPU, will know for sure
after i check the topology)
that can be achieved with
mpirun --map-by socket:span,PE=
I'd like to follow up to my own e-mail...
After playing around with the --bind-to options, it seems there is no
way to do this with AMD CMT processors, since they are actual physical
cores, and not hardware threads that appear as "logical cores" as with
Intel processors with hyperthreading. Wh
I don't know any reason why you shouldn't be able to use IB for intra-node
transfers. There are, of course, arguments against doing it in general
(e.g. IB/PCI bandwidth less than DDR4 bandwidth), but it likely behaves
less synchronously than shared-memory, since I'm not aware of any MPI RMA
librar
Jeff, all,
Thanks for the clarification. My measurements show that global memory
allocations do not require the backing file if there is only one process
per node, for arbitrary number of processes. So I was wondering if it
was possible to use the same allocation process even with multiple
pr
