Each CPU can have a different request into the PLL (phase locked loop),
but the highest one wins, and their vote does not count if they are in
an idle state deeper than C1. You can observe this manually by reading
the pstate request and granted MSRs directly (requires msr-tools, and
the msr module
There is only one PLL (Phase Locked Loop) in the processor, all CPUs get
the resulting clock. When they go into deep idle states (deeper than C1,
at least for my processor) then they give up their vote into the PLL as
to what the frequency should be. Your single 100% task is dedicating the
CPU freq
@Davide Sangalli: What you describe and show in your comment #80 is
correct and exactly what should happen. Your processor is spending an
extraordinary amount of time in C1 as opposed to deeper idle states. At
what sampling frequency do you run i7z? I would suggest once every 15
seconds or so, so t
Yes, this has fixed my problem for one of my 14.04 Desktop VM running on my
12.04 server host.
I have several other scenarios to check, it'll take me awhile. (I came here
from bug 1282342 , which started 2104.02.17)
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