Hello Alexey,
Alexey Brodkin wrote on 2014-01-15:
> "init_sequence_r" is just an array that consists of compile-time
> adresses of init functions. Since this is basically an array of integers
> (pointers to "void" to be more precise) it won't be modified during
> relocation - it will be just copie
Alexey Brodkin wrote on 2014-01-15:
> On Wed, 2014-01-15 at 11:27 +, thomas.lan...@lantiq.com wrote:
>> I think this is only required/possible for architectures which define
>> CONFIG_NEEDS_MANUAL_RELOC, others don't have "gd->reloc_off"
>>
>>> if (initcall_run_list(init_sequence_r))
>>>
Hello Hans,
Hans de Goede wrote on 2014-07-27:
> On some boards the phy needs to be powered up through a gpio, add
> support for this.
>
> @@ -129,6 +129,11 @@ int cpu_eth_init(bd_t *bis)
> {
> __maybe_unused int rc;
> +#ifdef CONFIG_MACPWR
If this is powering a phy, maybe CONFIG_PHYPWR
Hello Michal,
Michal Simek wrote on 2015-04-16:
> From: Siva Durga Prasad Paladugu
>
> Fix wrong timer calculation in get_timer_masked incase of overflow. This
> fixes the issue of getting wrong time from get_timer() calls.
>
> Signed-off-by: Siva Durga Prasad Paladugu
> Signed-off-by: Michal
Hello Maxime,
can you explain the usecase?
I think, only the erase is executed per sector, all other commands are working
fine with a byte oriented length.
Best regards,
Thomas
---
Sent from my phone.
Maxime Hadjinlian hat geschrieben:
This patch adds [+]len handler for the all the commands
> On Sunday, October 05, 2014 at 08:40:26 PM, Maxime Hadjinlian wrote:
> > Hi Thomas, all,
> >
> > On Sun, Oct 5, 2014 at 7:43 PM, wrote:
> > > Hello Maxime,
> > >
> > > can you explain the usecase?
> > > I think, only the erase is executed per sector, all other commands are
> > > working fine wi
Hello Daniel,
Daniel Schwierzeck wrote on 2011-11-25:
> On Fri, Nov 25, 2011 at 9:49 AM, Marek Vasut
> wrote:
>>> On Thursday 24 November 2011 08:57:56 Daniel Schwierzeck wrote:
Build dbau1550_el only in LIST_au1xx0_el and LIST_mips_el.
Also remove obsolete lists for mips5kc.
>>>
>>> i
Hi Daniel,
Daniel Schwierzeck wrote on 2011-07-27:
> This patch series contains cleanups and enhancements to consolidate
> the INCA-IP related config options and to make them more generic.
> Additionally, the cache operation mode is now configurable.
> All changes are needed to prepare the suppor
Hi,
I'm in the process of preparing some code for a new board and want to use the
generic cfi flash driver. The problem is EBU (External Bus Unit) of the chip,
which is internally 32bit.
The access to 8/16bit values are always mapped by the EBU, but in a little
endian way, which is bad on a big e
> In message <200903261103.28452...@denx.de> you wrote:
> >
> > > #define FLASH_FIXUP_ADDR_8(addr) ((void*)((ulong)(addr)^2))
> > > #define FLASH_FIXUP_ADDR_16(addr) ((void*)((ulong)(addr)^2))
> ...
> > Yes, I think this could be accepted. The overall impact on
> the driver is not
> > too big.
Hello Mike,
> + union {
> + u32 enetaddr32;
> + u16 enetaddr16[3];
> + unsigned char enetaddr[6];
> + };
This will work only as long the endianess is matching.
Picking single chars from enetaddr[] and combine them to a u32 register
will be more indepen
Hello Jagan,
Am 24.09.2013 20:38, schrieb Jagannadha Sutradharudu Teki:
> This patch series is a combination of
> "sf: Add common probe support"
> "sf: Add support for extended/quad read and write commands"
> http://www.mail-archive.com/u-boot@lists.denx.de/msg121668.html
> http://u-boot.10912.n7.
Hello Jagan,
Am 24.09.2013 20:36, schrieb Jagannadha Sutradharudu Teki:
> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> index ea39d1a..0ac9fab 100644
> --- a/drivers/spi/spi.c
> +++ b/drivers/spi/spi.c
> @@ -7,6 +7,7 @@
> #include
> #include
> #include
> +#include
>
> void *spi_do
Hello Jagan,
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Wednesday, September 25, 2013 11:36 AM
> To: Langer Thomas (LQDE RD ST PON SW)
> Cc: Jagannadha Sutradharudu Teki; Tom Rini; jaganna; u-boot@lists.denx.de;
> Todd Legler (tlegler); Willis Max; Syed Hussain; Sascha Silbe
> Su
Hello Jagan,
Jagan Teki wrote on 2013-09-25:
> On Wed, Sep 25, 2013 at 3:14 PM, wrote:
>> Hello Jagan,
>>
>>> From: Jagan Teki [mailto:jagannadh.t...@gmail.com] Sent: Wednesday,
>>> September 25, 2013 11:36 AM To: Langer Thomas (LQDE RD ST PON SW) Cc:
>>> Jagannadha Sutradharudu Teki; Tom Rini;
Hello Jagan,
Jagan Teki wrote on 2013-09-25:
> Thanks for your comments, see below
>
> On Wed, Sep 25, 2013 at 1:02 AM, wrote:
>> Hello Jagan,
>>
>> Am 24.09.2013 20:38, schrieb Jagannadha Sutradharudu Teki:
>>> This patch series is a combination of "sf: Add common probe support"
>>> "sf: Add
Hello Jagan,
Jagan Teki wrote on 2013-09-25:
> On Wed, Sep 25, 2013 at 3:34 PM, wrote:
>> Hello Jagan,
>>
>> Jagan Teki wrote on 2013-09-25:
>>> On Wed, Sep 25, 2013 at 3:14 PM, wrote:
Hello Jagan,
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com] Sent: Wednesday,
> Septem
Hello Jagan,
it seems an almost ready patch for m25p80 driver in the kernel was posted today:
"[PATCHv2] drivers: mtd: devices: Add quad read support."
http://thread.gmane.org/gmane.linux.drivers.mtd/48552/focus=48557
Please see how there in the function "m25p80_quad_read"
the "rx_nbits" in the t
Hello Jagan,
I have some comments and questions:
Am 05.11.2013 18:51, schrieb Jagannadha Sutradharudu Teki:
> +
> +/* Definitions of the flash commands - Flash insts in ascending order */
> +#define ZYNQ_QSPI_FLASH_INST_WRSR0x01/* Write status register */
> +#define ZYNQ_QSPI_FLASH_INST_P
Hi Jagan,
> +
> +/* Definitions of the flash commands - Flash insts in ascending order */
> +#define ZYNQ_QSPI_FLASH_INST_WRSR0x01/* Write status register */
> +#define ZYNQ_QSPI_FLASH_INST_PP 0x02/* Page program */
> +#define ZYNQ_QSPI_FLASH_INST_WRDS0x04/* Write
Hello Prabhakar,
Prabhakar Kushwaha wrote on 2013-08-16:
> 85xx, 86xx PowerPC folders have code variables with CamelCase naming
> conventions. because of this code checkpatch script generates "WARNING:
> Avoid CamelCase".
>
> This patch set Convert variables name to normal naming convention and
>
Hello Stefano,
Stefano Babic wrote on 2013-09-02:
> Some phys have additional registers that are not covered
> by standard. Access to this registers can be done via
> specific sequence according to the phy datasheet.
> The driver for Micrel phy contains some additional function,
> that the board
Hello Tom,
> Note that ARM provides arch_fixup_memory_node to make sure we have all
> of the bank information populated and then calls fdt_fixup_memory_banks,
> while PowerPC just calls fdt_fixup_memory which calls banks with a '1'
> for number of banks. MIPS (and everyone else) isn't doing anyth
This patch fixes problems in the handling of redundant environment in env_sf.c
The major problem are double calls of free() on the allocated buffers,
which damages the internal data of malloc and crashes on next call.
In addition, the selection of the active environment had errors and compiler
w
Hello Wolfgang,
Wolfgang Denk wrote on 2015-07-15:
> 2. For some time now, we provide not only the classic FTP server for
>download of the U-Boot release tarballs, but also a public
>directory in the Amazon Cloud Drive [1]. The ACD is supposed to
>provide much better connectivity (es
Hello Stephen,
>> diff --git a/include/configs/chromeos.h b/include/configs/chromeos.h
>>
>> +/* Stringify a token */
>> +#ifndef STRINGIFY
>> +#define _STRINGIFY(x) #x
>> +#define STRINGIFY(x)_STRINGIFY(x)
>> +#endif
>
> Shouldn't that be in some common header so it isn't ever dup
From: Thomas Langer
The common code just needs the C0_COUNT as free running counter,
without the need of writing and checking C0_COMPARE.
The function get_tbclk() is still implemented here instead of changing
all places of CONFIG_SYS_MIPS_TIMER_FREQ to CONFIG_SYS_TIMER_RATE.
The change was test
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