[PATCHv1 0/2] Enable the 'cpu' command for i.MX8M series EVK boards

From: Hou Zhiqiang This patch set is to enable the 'cpu' command for i.MX8M Plus, Mini and Nano EVK, so that it can kick one CPU core to run the barematel or RTOS applicatons under U-Boot. Hou Zhiqiang (1): mp: imx8m: add cpu command support Jiafei Pan (1): mp: imx8m: enable CONFIG_MP to su

[PATCHv1 2/2] mp: imx8m: enable CONFIG_MP to support cpu command

From: Jiafei Pan Enable the cpu command support for the default config. Signed-off-by: Jiafei Pan Signed-off-by: Hou Zhiqiang --- configs/imx8mm_evk_defconfig | 1 + configs/imx8mn_ddr4_evk_defconfig | 1 + configs/imx8mp_evk_defconfig | 1 + 3 files changed, 3 insertions(+) diff -

[PATCHv1 1/2] mp: imx8m: add cpu command support

From: Hou Zhiqiang Implement the cpu command to kick cpu core to run barematel or RTOS applications. Signed-off-by: Hou Zhiqiang Signed-off-by: Yi Zhao Signed-off-by: Jiafei Pan --- arch/arm/mach-imx/imx8m/Makefile | 3 +- arch/arm/mach-imx/imx8m/mp.c | 100

[PATCHv1 0/3] Enable the 'cpu' command for i.MX93 EVK board

From: Hou Zhiqiang This patch set is to enable the 'cpu' command for i.MX93 EVK, so that it can kick one CPU core to run the barematel or RTOS applicatons under U-Boot. Tao Yang (3): mp: imx9: add cpu command support imx93_evk: add definition CONFIG_MAX_CPUS configs: imx93-11x11-evk: enabl

[PATCHv1 1/3] mp: imx9: add cpu command support

From: Tao Yang Implement the cpu command to kick cpu core to run barematel or RTOS applications. Signed-off-by: Tao Yang Signed-off-by: Hou Zhiqiang --- arch/arm/mach-imx/imx9/Makefile | 4 +- arch/arm/mach-imx/imx9/mp.c | 81 + 2 files changed, 84 inserti

[PATCHv1 2/3] imx93_evk: add definition MAX_CPUS

From: Tao Yang Add definition for determining the implemented CPU numbers. Signed-off-by: Tao Yang Signed-off-by: Hou Zhiqiang --- include/configs/imx93_evk.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index

[PATCHv1 3/3] configs: imx93-11x11-evk: enable CONFIG_MP to support cpu command

From: Tao Yang Enable the cpu command support for the default config. Signed-off-by: Tao Yang Signed-off-by: Hou Zhiqiang --- configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 2246

[PATCHv1 0/5] Add a subcommand 'release' to cmd/cpu.c

From: Hou Zhiqiang This patch set is to add a subcommand 'release' to the 'cpu' command in cmd/cpu.c, making the command is able to release a core to run baremetal and RTOS applications. And enabled the 'cpu' command and imx CPU driver for i.MX 8M series EVK boards and i.MX 93 EVK board. Hou Zh

[PATCHv1 2/5] cpu: imx: implement release_core callback

From: Hou Zhiqiang Release the secondary cores through the PSCI request. Signed-off-by: Hou Zhiqiang --- drivers/cpu/imx8_cpu.c | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 4781a56554..5942a

[PATCHv1 4/5] configs: imx8m: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command and the depended imx CPU driver to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- configs/imx8mm_evk_defconfig | 3 +++ configs/imx8mn_evk_defconfig | 3 +++ configs/imx8mp_evk_defconf

[PATCHv1 5/5] configs: imx93: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx

[PATCHv1 3/5] cmd: cpu: add release subcommand

From: Hou Zhiqiang Add a new subcommand 'release' to bring up a core to run baremetal and RTOS applications. For example on i.MX8M Plus EVK, release the LAST core to run a RTOS application, passing the sequence number of the CPU core to release, here it is 3: u-boot=> cpu list 0: cpu@0

[PATCHv1 1/5] cpu: add release_core callback

From: Hou Zhiqiang Add a new callback release_core to the cpu_ops, which is used to release a CPU core to run baremetal or RTOS application on a SoC with multiple CPU cores. Signed-off-by: Hou Zhiqiang --- drivers/cpu/cpu-uclass.c | 10 ++ include/cpu.h| 15 +++

[PATCH] clk: fix ccf_clk_get_rate

From: Hou Zhiqiang As the type of return value is 'ulong', when clk_get_by_id() failed, it should return 0 to indicate the get_rate operation doesn't succeed. Signed-off-by: Hou Zhiqiang --- drivers/clk/clk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk

[PATCH] clk: imx8m: register ARM A55 core clock

From: Hou Zhiqiang Register ARM A55 core clock for i.MX 8M Mini, Nano and Plus. Signed-off-by: Hou Zhiqiang --- drivers/clk/imx/clk-imx8mm.c | 6 ++ drivers/clk/imx/clk-imx8mn.c | 7 +++ drivers/clk/imx/clk-imx8mp.c | 7 +++ 3 files changed, 20 insertions(+) diff --git a/drivers/c

[PATCHv2 0/9] Add a subcommand 'release' to cmd/cpu.c

From: Hou Zhiqiang This patch set is to add a subcommand 'release' to the 'cpu' command in cmd/cpu.c, making the command is able to release a core to run baremetal and RTOS applications. And enabled the 'cpu' command and imx CPU driver for i.MX 8M series EVK boards and i.MX 93 EVK board. depend

[PATCHv2 1/9] cpu: add release_core callback

From: Hou Zhiqiang Add a new callback release_core to the cpu_ops, which is used to release a CPU core to run baremetal or RTOS application on a SoC with multiple CPU cores. Signed-off-by: Hou Zhiqiang --- V2: - No change. drivers/cpu/cpu-uclass.c | 10 ++ include/cpu.h|

[PATCHv2 2/9] cpu: sandbox: implement release_core callback

From: Hou Zhiqiang Add empty release CPU core function for testing. Signed-off-by: Hou Zhiqiang --- V2: - New patch. drivers/cpu/cpu_sandbox.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c index e65e1bdc51b..b1527957831 100644

[PATCHv2 3/9] test: cpu: add test for release CPU core.

From: Hou Zhiqiang Add test for API cpu_release_core(). Signed-off-by: Hou Zhiqiang --- V2: - New patch. test/dm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test/dm/cpu.c b/test/dm/cpu.c index acba8105996..8af25316cea 100644 --- a/test/dm/cpu.c +++ b/test/dm/cpu.c @@ -43,6 +4

[PATCHv2 4/9] cpu: imx: implement release_core callback

From: Hou Zhiqiang Release the secondary cores through the PSCI request. Signed-off-by: Hou Zhiqiang --- V2: - No change. drivers/cpu/imx8_cpu.c | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c inde

[PATCHv2 5/9] cpu: imx: fix the CPU type field width

From: Hou Zhiqiang Increase one more bit to cover all CPU types. Otherwise it shows wrong CPU info on some platforms, such as i.MX8M Plus: U-Boot 2024.04+g674440bc73e+p0 (Jun 06 2024 - 10:05:34 +) CPU: NXP i.MX8MM Rev1.1 A53 at 4154504685 MHz at 30C Model: NXP i.MX8MPlus LPDD

[PATCHv2 6/9] cpu: imx: Add i.MX 8M series SoCs

From: Hou Zhiqiang Add i.MX 8M Mini, Nano and Plus SoCs support. Signed-off-by: Hou Zhiqiang --- V2: - New patch. drivers/cpu/imx8_cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 0509becf91e..dfedc9ffd14 100644 --- a/drive

[PATCHv2 7/9] cmd: cpu: add release subcommand

From: Hou Zhiqiang Add a new subcommand 'release' to bring up a core to run baremetal and RTOS applications. For example on i.MX8M Plus EVK, release the LAST core to run a RTOS application, passing the sequence number of the CPU core to release, here it is 3: u-boot=> cpu list 0: cpu@0

[PATCHv2 8/9] configs: imx8m: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command and the depended imx CPU driver to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- V2: - No change. configs/imx8mm_evk_defconfig | 3 +++ configs/imx8mn_evk_defconfig | 3 +++ configs

[PATCHv2 9/9] configs: imx93: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- V2: - No change. configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx93_11x11_evk_defco

[PATCHv2] clk: imx8m: register ARM A53 core clock

From: Hou Zhiqiang Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus. Signed-off-by: Hou Zhiqiang --- V2: - Fixed the change log: s/A55/A53 drivers/clk/imx/clk-imx8mm.c | 6 ++ drivers/clk/imx/clk-imx8mn.c | 7 +++ drivers/clk/imx/clk-imx8mp.c | 7 +++ 3 files changed,

[PATCHv3 0/12] Add a subcommand 'release' to cmd/cpu.c

From: Hou Zhiqiang This patch set is to add a subcommand 'release' to the 'cpu' command in cmd/cpu.c, making the command is able to release a core to run baremetal and RTOS applications. Fixed some problems of the imx8_cpu.c and added i.MX 8M series SoCs support. And enabled the 'cpu' command a

[PATCHv3 01/12] cpu: add release_core callback

From: Hou Zhiqiang Add a new callback release_core to the cpu_ops, which is used to release a CPU core to run baremetal or RTOS application on a SoC with multiple CPU cores. Signed-off-by: Hou Zhiqiang --- V3: - No change. drivers/cpu/cpu-uclass.c | 10 ++ include/cpu.h|

[PATCHv3 02/12] cpu: sandbox: implement release_core callback

From: Hou Zhiqiang Add empty release CPU core function for testing. Signed-off-by: Hou Zhiqiang --- V3: - No change. drivers/cpu/cpu_sandbox.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c index e65e1bdc51b..b1527957831 100644

[PATCHv3 03/12] test: cpu: add test for release CPU core.

From: Hou Zhiqiang Add test for API cpu_release_core(). Signed-off-by: Hou Zhiqiang --- V3: - No change. test/dm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test/dm/cpu.c b/test/dm/cpu.c index acba8105996..8af25316cea 100644 --- a/test/dm/cpu.c +++ b/test/dm/cpu.c @@ -43,6 +4

[PATCHv3 04/12] cpu: imx: fix the CPU frequency in cpu_imx_get_info()

From: Hou Zhiqiang 1MHz = 100Hzz Signed-off-by: Hou Zhiqiang --- V3: - New patch. drivers/cpu/imx8_cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 4781a565547..601a7071a64 100644 --- a/drivers/cpu/imx

[PATCHv3 05/12] cpu: imx: fix the CPU type field width

From: Hou Zhiqiang Increase one more bit to cover all CPU types. Otherwise it shows wrong CPU info on some platforms, such as i.MX8M Plus: U-Boot 2024.04+g674440bc73e+p0 (Jun 06 2024 - 10:05:34 +) CPU: NXP i.MX8MM Rev1.1 A53 at 4154504685 MHz at 30C Model: NXP i.MX8MPlus LPDD

[PATCHv3 06/12] cpu: imx: Add i.MX 8M series SoCs

From: Hou Zhiqiang Add i.MX 8M Mini, Nano and Plus SoCs support. Signed-off-by: Hou Zhiqiang --- V3: - No change. drivers/cpu/imx8_cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 6a97b7b9ad0..c1315cc32dd 100644 --- a/drive

[PATCHv3 08/12] cmd: cpu: add release subcommand

From: Hou Zhiqiang Add a new subcommand 'release' to bring up a core to run baremetal and RTOS applications. For example on i.MX8M Plus EVK, release the LAST core to run a RTOS application, passing the sequence number of the CPU core to release, here it is 3: u-boot=> cpu list 0: cpu@0

[PATCHv3 07/12] cpu: imx: implement release_core callback

From: Hou Zhiqiang Release the secondary cores through the PSCI request. Signed-off-by: Hou Zhiqiang --- V3: - No change. drivers/cpu/imx8_cpu.c | 24 1 file changed, 24 insertions(+) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index c1315cc32dd..85

[PATCHv3 09/12] doc: cmd: add documentation for cpu command

From: Hou Zhiqiang Add documentation for the 'cpu' command, taking NXP i.MX 8M Plus as a example. Signed-off-by: Hou Zhiqiang --- V3: - New patch. doc/usage/cmd/cpu.rst | 82 +++ 1 file changed, 82 insertions(+) create mode 100644 doc/usage/cmd/cpu.rs

[PATCHv3 10/12] MAINTAINERS: add entry for cpu command

From: Hou Zhiqiang Added the original author Simon and myself. Signed-off-by: Hou Zhiqiang --- V3: - New patch. MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a6e47e8a217..f1aa802758d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -996,6

[PATCHv3 11/12] configs: imx8m: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command and the depended imx CPU driver to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- V3: - No change. configs/imx8mm_evk_defconfig | 3 +++ configs/imx8mn_evk_defconfig | 3 +++ configs

[PATCHv3 12/12] configs: imx93: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- V3: - No change. configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx93_11x11_evk_defco

[PATCHv3 00/14] Add a subcommand 'release' to cmd/cpu.c

From: Hou Zhiqiang This patch set is to add a subcommand 'release' to the 'cpu' command in cmd/cpu.c, making the command is able to release a core to run baremetal and RTOS applications. Fixed some problems of the imx8_cpu.c and added i.MX 8M series SoCs support. Added ARM A53 core clock regist

[PATCHv4 01/14] clk: imx8m: register ARM A53 core clock

From: Hou Zhiqiang Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus, preparing for enabling the 'cpu' command, which depends on this to print CPU core frequency. Signed-off-by: Hou Zhiqiang --- V4: - Moved here from other thread. drivers/clk/imx/clk-imx8mm.c | 6 ++ drivers/cl

[PATCHv4 02/14] cpu: add release_core callback

From: Hou Zhiqiang Add a new callback release_core to the cpu_ops, which is used to release a CPU core to run baremetal or RTOS application on a SoC with multiple CPU cores. Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass --- V4: - No change. drivers/cpu/cpu-uclass.c | 10 ++ i

[PATCHv4 03/14] cpu: sandbox: implement release_core callback

From: Hou Zhiqiang Add empty release CPU core function for testing. Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass --- V4: - No change. drivers/cpu/cpu_sandbox.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c index e65e1

[PATCHv4 04/14] test: cpu: add test for release CPU core.

From: Hou Zhiqiang Add test for API cpu_release_core(). Signed-off-by: Hou Zhiqiang Reviewed-by: Simon Glass --- V4: - No change. test/dm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test/dm/cpu.c b/test/dm/cpu.c index acba810599..8af25316ce 100644 --- a/test/dm/cpu.c +++ b/t

[PATCHv4 05/14] cpu: imx: fix the CPU frequency in cpu_imx_get_info()

From: Hou Zhiqiang The cpu_freq stores the current CPU frequency in Hz. Signed-off-by: Hou Zhiqiang --- V4: - Rewrote the change log. drivers/cpu/imx8_cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 4781a5655

[PATCHv4 06/14] cpu: imx: fix the CPU type field width

From: Hou Zhiqiang Increase one more bit to cover all CPU types. Otherwise it shows wrong CPU info on some platforms, such as i.MX8M Plus: U-Boot 2024.04+g674440bc73e+p0 (Jun 06 2024 - 10:05:34 +) CPU: NXP i.MX8MM Rev1.1 A53 at 4154504685 MHz at 30C Model: NXP i.MX8MPlus LPDD

[PATCHv4 07/14] cpu: imx: removed the tail '\n' of the CPU description

From: Hou Zhiqiang Return CPU description string without newline character in the end. Signed-off-by: Hou Zhiqiang --- V4: - New patch. drivers/cpu/imx8_cpu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 6a97b7b9ad..b633a2c73a 100

[PATCHv4 08/14] cpu: imx: Add i.MX 8M series SoCs

From: Hou Zhiqiang Add i.MX 8M Mini, Nano and Plus SoCs support. Signed-off-by: Hou Zhiqiang --- V4: - No change. drivers/cpu/imx8_cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index b633a2c73a..a35147b72a 100644 --- a/drivers

[PATCHv4 09/14] cpu: imx: implement release_core callback

From: Hou Zhiqiang Release the secondary cores through the PSCI request. Signed-off-by: Hou Zhiqiang --- V4: - No change. drivers/cpu/imx8_cpu.c | 24 1 file changed, 24 insertions(+) diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index a35147b72a..60d

[PATCHv4 10/14] cmd: cpu: add release subcommand

From: Hou Zhiqiang Add a new subcommand 'release' to bring up a core to run baremetal and RTOS applications. For example on i.MX8M Plus EVK, release the LAST core to run a RTOS application, passing the sequence number of the CPU core to release, here it is 3: u-boot=> cpu list 0: cpu@0

[PATCHv4 11/14] doc: cmd: add documentation for cpu command

From: Hou Zhiqiang Add documentation for the 'cpu' command, taking NXP i.MX 8M Plus as a example. Signed-off-by: Hou Zhiqiang --- V4: - Added brief descriptions for each subcommand.. doc/usage/cmd/cpu.rst | 101 ++ 1 file changed, 101 insertions(+) cr

[PATCHv4 12/14] MAINTAINERS: add entry for cpu command

From: Hou Zhiqiang Added the original author Simon and myself. Signed-off-by: Hou Zhiqiang --- V4: - No change. MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a6e47e8a21..f1aa802758 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -996,6 +

[PATCHv4 13/14] configs: imx8m: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command and the depended imx CPU driver to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- V4: - No change. configs/imx8mm_evk_defconfig | 3 +++ configs/imx8mn_evk_defconfig | 3 +++ configs

[PATCHv4 14/14] configs: imx93: enable the 'cpu' command

From: Hou Zhiqiang Enable the 'cpu' command to display the CPU info and release CPU core to run baremetal or RTOS applications. Signed-off-by: Hou Zhiqiang --- V4: - No change. configs/imx93_11x11_evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imx93_11x11_evk_defco

[PATCH] pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2

From: Hou Zhiqiang LX2160A rev2 uses different PCIe controller, so EP mode DT nodes also need to be fixed up. Signed-off-by: Hou Zhiqiang --- drivers/pci/pcie_layerscape_fixup_common.c | 26 ++ 1 file changed, 26 insertions(+) diff --git a/drivers/pci/pcie_layerscape_fixup

[PATCH] pci: layerscape: Change to allocate zeroed memery for struct ls_pcie

From: Hou Zhiqiang As on some incipient Layerscape platforms (LS1043A series) there isn't separate PF control register block, these registers reside in the LUT register block, so when the driver detected there isn't 'ctrl', it will assign the 'lut' address to the ls_pcie->ctrl. The current code

[PATCH 3/3] net: tsec: Access TBI PHY through the corresponding MII

From: Hou Zhiqiang When an eTSEC is configured to use TBI, configuration of the TBI is done through the MIIM registers for that eTSEC. For example, if a TBI interface is required on eTSEC2, then the MIIM registers starting at offset 0x2_5520 are used to configure it. Fixes: 9a1d6af55ecd ("net: t

[PATCH 2/3] net: tsec: Access eTSEC registers using virtual address

From: Hou Zhiqiang The current code accesses eTSEC registers using physical address directly, it's not correct, though no problem on current platforms. It won't work on platforms, which does not support 1:1 virtual-physical address map. Signed-off-by: Hou Zhiqiang --- drivers/net/tsec.c | 9 ++

[PATCH 1/3] doc: dt-bindings: tsec: Correct the Ethernet port compatible string

From: Hou Zhiqiang Change the compatible string to "fsl,etsec2" for the Ethernet ports, which is used in the current driver's match table. Fixes: 69a00875e3db ("doc: dt-bindings: Describe Freescale TSEC ethernet controller") Signed-off-by: Hou Zhiqiang --- doc/device-tree-bindings/net/fsl-tse

[PATCH 0/3] net: tsec: Fix issues of DM driver

From: Hou Zhiqiang This patch set is to fix some issues of eTSEC DM driver. Hou Zhiqiang (3): doc: dt-bindings: tsec: Correct the Ethernet port compatible string net: tsec: Access eTSEC registers using virtual address net: tsec: Access TBI PHY through the corresponding MII doc/device-tre

[PATCHv2 1/3] doc: dt-bindings: tsec: Correct the Ethernet port compatible string

From: Hou Zhiqiang Change the compatible string to "fsl,etsec2" for the Ethernet ports, which is used in the current driver's match table. Fixes: 69a00875e3db ("doc: dt-bindings: Describe Freescale TSEC ethernet controller") Signed-off-by: Hou Zhiqiang Acked-by: Vladimir Oltean --- V2: - No

[PATCHv2 2/3] net: tsec: Access eTSEC registers using virtual address

From: Hou Zhiqiang The current code accesses eTSEC registers using physical address directly, it's not correct, though no problem on current platforms. It won't work on platforms, which does not support 1:1 virtual-physical address map. Signed-off-by: Hou Zhiqiang Reviewed-by: Vladimir Oltean

[PATCHv2 0/3] net: tsec: Fix issues of DM driver

From: Hou Zhiqiang This patch set is to fix some issues of eTSEC DM driver. Hou Zhiqiang (3): doc: dt-bindings: tsec: Correct the Ethernet port compatible string net: tsec: Access eTSEC registers using virtual address net: tsec: Access TBI PHY through the corresponding MII doc/device-tre

[PATCHv2 3/3] net: tsec: Access TBI PHY through the corresponding MII

From: Hou Zhiqiang When an eTSEC is configured to use TBI, configuration of the TBI is done through the MIIM registers for that eTSEC. For example, if a TBI interface is required on eTSEC2, then the MIIM registers starting at offset 0x2_5520 are used to configure it. Fixes: 9a1d6af55ecd ("net: t

[PATCH 01/13] net: fsl_pq_mdio: Add the compatible "fsl, gianfar-mdio" support

From: Hou Zhiqiang Add compatible string "fsl,gianfar-mdio" support and update the device-tree-bindings doc. Signed-off-by: Hou Zhiqiang --- doc/device-tree-bindings/net/fsl-tsec-phy.txt | 3 ++- drivers/net/fsl_mdio.c| 15 +-- include/fsl_mdio.h

[PATCH 02/13] net: tsec: Add the compatible string "gianfar" support

From: Hou Zhiqiang Add compatible string "gianfar" support and update the device-tree-bindings doc. Signed-off-by: Hou Zhiqiang --- doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +- drivers/net/tsec.c| 16 ++-- include/tsec.h

[PATCH 04/13] fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r()

From: Hou Zhiqiang Move vsc7835 firmware uploading to board_early_init_r(), so that the switch also can work in DM eTSEC driver. Signed-off-by: Hou Zhiqiang --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 35 +++-- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git

[PATCH 00/13] powerpc: covert p1010, p1020 and p2020 RDB board

From: Hou Zhiqiang This patch set depends on: https://patchwork.ozlabs.org/project/uboot/list/?series=174343 Hou Zhiqiang (13): net: fsl_pq_mdio: Add the compatible "fsl,gianfar-mdio" support net: tsec: Add the compatible string "gianfar" support powerpc: mpc8xxx: Don't compile cpu_eth_ini

[PATCH 08/13] configs: P1020RDB: Enable DM_ETH config

From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. On P1020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support. Signed-off-by: Hou Zhiqiang --- configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 3 ++

[PATCH 03/13] powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled

From: Hou Zhiqiang The cpu_eth_init() is only used by the legacy ethernet driver framework. Signed-off-by: Hou Zhiqiang --- arch/powerpc/cpu/mpc8xxx/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index ed482a9c09..d41

[PATCH 05/13] configs: p1_p2_rdb: Add the default address of vsc7385 firmware

From: Hou Zhiqiang Add the environment 'vscfw_addr' to assign a default address for vsc7385 firmware uploading. Signed-off-by: Hou Zhiqiang --- include/configs/p1_p2_rdb_pc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h i

[PATCH 07/13] powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled

From: Hou Zhiqiang The board_eth_init() is only used by legacy ethernet driver framework, so do not compile it when DM_ETH config has been selected. Signed-off-by: Hou Zhiqiang --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale

[PATCH 06/13] dts: powerpc: p1020rdb: Add eTSEC DT nodes

From: Hou Zhiqiang P1020RDB implements 3 enhanced three-speed Ethernet controllers, and the connection is shown below: eTSEC1: Connected to RGMII PHY VSC7385 eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY AR8021 Signed-off-by: Hou Zhiqiang --- arch/powerpc/dt

[PATCH 12/13] dts: powerpc: p2020rdb: Add eTSEC DT nodes

From: Hou Zhiqiang P2020RDB implements 3 enhanced three-speed Ethernet controllers, and the connection is shown below: eTSEC1: Connected to RGMII PHY VSC7385 eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY AR8021 Signed-off-by: Hou Zhiqiang --- arch/powerpc/dt

[PATCH 11/13] configs: P1010RDB: Enable DM_ETH config

From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. Signed-off-by: Hou Zhiqiang --- configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig |

[PATCH 13/13] configs: P2020RDB: Enable DM_ETH config

From: Hou Zhiqiang Enable the DM_ETH and DM_MDIO config. On P2020RDB, the eTSEC1 is connecting with a switch VSC7385, so also enable the fixed PHY support. Signed-off-by: Hou Zhiqiang --- configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 +++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 ++

[PATCH 10/13] powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH

From: Hou Zhiqiang The board_eth_init() is only used by legacy ethernet driver framework, so do not compile it when DM_ETH config has been selected. Signed-off-by: Hou Zhiqiang --- board/freescale/p1010rdb/p1010rdb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale/p1010rd

[PATCH 09/13] dts: powerpc: p1010rdb: Add eTSEC DT nodes

From: Hou Zhiqiang P1010RDB implements 3 enhanced three-speed Ethernet controllers, and the connection is shown below: eTSEC1: Connected to RGMII PHY AR8033 eTSEC2: Connected to SGMII PHY AR8033 eTSEC3: Connected to SGMII PHY AR8033 Signed-off-by: Hou Zhiqiang --- arch/powerpc/dts/

[PATCH 00/12] fsl: layerscape: Initialize the GIC redistributor

From: Hou Zhiqiang This patch set is to initialize the GIC redistributor tables and add the tables to kernel DT's reserved memeory node. Hou Zhiqiang (12): board: lx2160a: Add header file cpu_func.h arm64: fsl-layerscape: Assign addr to resv_ram if enabled RESV_RAM config arm64: layers

[PATCH 02/12] arm64: fsl-layerscape: Assign addr to resv_ram if enabled RESV_RAM config

From: Hou Zhiqiang The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-laye

[PATCH 01/12] board: lx2160a: Add header file cpu_func.h

From: Hou Zhiqiang The declaration of the function cpu_numcores() has been moved to cpu_func.h, so add including of the header file to avoid build error. Signed-off-by: Hou Zhiqiang --- board/freescale/lx2160a/lx2160a.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/lx2160

[PATCH 04/12] board: lx2160a: Don't program the GIC RD tables if failed to reserve memory

From: Hou Zhiqiang Program the GIC redistributor tables only when succeeded to reserve memory for them, otherwise kernel will lose the chance to program them using allocated memory. Signed-off-by: Hou Zhiqiang --- board/freescale/lx2160a/lx2160a.c | 8 ++-- 1 file changed, 6 insertions(+),

[PATCH 05/12] board: lx2160a: Make sure the RD tables address align to 64KB

From: Hou Zhiqiang As the lower 16bit of the redistributor pending table is reserved for describing the memory attributes, we must give a 64KB aligned address to the GIC LPI initialization function. Signed-off-by: Hou Zhiqiang --- board/freescale/lx2160a/lx2160a.c | 3 ++- 1 file changed, 2 in

[PATCH 03/12] arm64: layerscape: Move the GIC tables reserve memory function to soc.c

From: Hou Zhiqiang Move the function of reserving memory for GIC redistributor tables to soc.c, such that other Layerscape platform can leverage it, and add a argument for the memory size to reserve. And rename the function so that it is more readable. Signed-off-by: Hou Zhiqiang --- arch/arm/

[PATCH 08/12] configs: ls1088a: Enable GIC_V3_ITS config

From: Hou Zhiqiang Enable GIC_V3_ITS config to initialize the GIC redistributor tables. Signed-off-by: Hou Zhiqiang --- configs/ls1088aqds_defconfig | 1 + configs/ls1088aqds_qspi_SECURE_BOOT_defconfig| 1 + configs/ls1088aqds_qspi_defconfig|

[PATCH 07/12] board: fsl: ls1088a: Initialize the GIC redistributor tables

From: Hou Zhiqiang Fixup kernel DT to reserve memory for GIC redistributor tables, and initialize the redistributor configuration and pending tables using the reserved memory. Signed-off-by: Hou Zhiqiang --- board/freescale/ls1088a/ls1088a.c | 15 +++ 1 file changed, 15 insertions(

[PATCH 06/12] fsl-layerscape: Kconfig: Select RESV_RAM config if GIC_V3_ITS is enabled

From: Hou Zhiqiang The GIC redistributor tables initialization depends on RESV_RAM config, so select RESV_RAM if GIC_V3_ITS is enabled. Signed-off-by: Hou Zhiqiang --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layer

[PATCH 11/12] board: fsl: ls2080a: Initialize the GIC redistributor tables

From: Hou Zhiqiang Fixup kernel DT to reserve memory for GIC redistributor tables, and initialize the redistributor configuration and pending tables using the reserved memory. Signed-off-by: Hou Zhiqiang --- board/freescale/ls2080aqds/ls2080aqds.c | 14 ++ board/freescale/ls2080ard

[PATCH 09/12] board: fsl: ls1028a: Initialize the GIC redistributor tables

From: Hou Zhiqiang Fixup kernel DT to reserve memory for GIC redistributor tables, and initialize the redistributor configuration and pending tables using the reserved memory. Signed-off-by: Hou Zhiqiang --- board/freescale/ls1028a/ls1028a.c | 14 ++ 1 file changed, 14 insertions(+

[PATCH 10/12] configs: ls1028a: Enable GIC_V3_ITS config

From: Hou Zhiqiang Enable GIC_V3_ITS config to initialize the GIC redistributor tables. Signed-off-by: Hou Zhiqiang --- configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028aqds_tfa_defconfig | 1 + configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1028ardb

[PATCH 12/12] configs: ls208xa: Enable GIC_V3_ITS config

From: Hou Zhiqiang Enable GIC_V3_ITS config to initialize the GIC redistributor tables. Signed-off-by: Hou Zhiqiang --- configs/ls2080aqds_SECURE_BOOT_defconfig | 1 + configs/ls2080aqds_defconfig | 1 + configs/ls2080aqds_nand_defconfig | 1 + configs/ls2080a

[PATCHv2 1/9] board: lx2160a: Add header file cpu_func.h

From: Hou Zhiqiang The declaration of the function cpu_numcores() has been moved to cpu_func.h, so add including of the header file to avoid build error. Signed-off-by: Hou Zhiqiang --- V2: - No change. board/freescale/lx2160a/lx2160a.c | 1 + 1 file changed, 1 insertion(+) diff --git a/boa

[PATCHv2 2/9] arm64: fsl-layerscape: Assign addr to resv_ram if enabled RESV_RAM config

From: Hou Zhiqiang The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by: Hou Zhiqiang --- V2: - No change. arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm

[PATCHv2 0/9] fsl: layerscape: Initialize the GIC redistributor

From: Hou Zhiqiang This patch set is to initialize the GIC redistributor tables and add the tables to kernel DT's reserved memeory node. Hou Zhiqiang (9): board: lx2160a: Add header file cpu_func.h arm64: fsl-layerscape: Assign addr to resv_ram if enabled RESV_RAM config board: lx2160a

[PATCHv2 3/9] board: lx2160a: Don't program the GIC RD tables if failed to reserve memory

From: Hou Zhiqiang Program the GIC redistributor tables only when succeeded to reserve memory for them, otherwise kernel will lose the chance to program them using allocated memory. Signed-off-by: Hou Zhiqiang --- V2: - The #4 of v1 patchset. board/freescale/lx2160a/lx2160a.c | 6 -- 1 f

[PATCHv2 7/9] configs: ls1088a: Enable GIC_V3_ITS config

From: Hou Zhiqiang Enable GIC_V3_ITS config to initialize the GIC redistributor tables. Signed-off-by: Hou Zhiqiang --- V2: - No change. configs/ls1088aqds_defconfig | 1 + configs/ls1088aqds_qspi_SECURE_BOOT_defconfig| 1 + configs/ls1088aqds_qspi_defconfig

[PATCHv2 4/9] board: lx2160a: Make sure the RD tables address align to 64KB

From: Hou Zhiqiang As the lower 16bit of the redistributor pending table is reserved for describing the memory attributes, we must give a 64KB aligned address to the GIC LPI initialization function. Signed-off-by: Hou Zhiqiang --- V2: - The #5 of v1 patchset. board/freescale/lx2160a/lx2160a.

[PATCHv2 5/9] fsl-layerscape: Kconfig: Select RESV_RAM config if GIC_V3_ITS is enabled

From: Hou Zhiqiang The GIC redistributor tables initialization depends on RESV_RAM config, so select RESV_RAM if GIC_V3_ITS is enabled. Signed-off-by: Hou Zhiqiang --- V2: - The #6 of v1 patchset. arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 1 file changed, 4 insertions(+) diff --git

[PATCHv2 6/9] arm64: layerscape: Move GIC RD tables initialization to CPU setup function

From: Hou Zhiqiang Move GIC redistributor tables initialization to CPU setup function. This patch introduces a GIC redistributor tables init function, and moves the function of reserving memory for GIC redistributor tables to soc.c and adds a argument for the memory size to reserve, BTW rename t

[PATCHv2 9/9] configs: ls208xa: Enable GIC_V3_ITS config

From: Hou Zhiqiang Enable GIC_V3_ITS config to initialize the GIC redistributor tables. Signed-off-by: Hou Zhiqiang --- V2: - No change. configs/ls2080aqds_SECURE_BOOT_defconfig | 1 + configs/ls2080aqds_defconfig | 1 + configs/ls2080aqds_nand_defconfig | 1

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