On 7/25/2023 1:34 AM, Fabio Estevam wrote:
On Mon, Jul 24, 2023 at 2:32 PM Yang Xiwen via B4 Relay
wrote:
From: Yang Xiwen
As described by the doc.
Which doc? Please mention the details in the commit log.
It's in the source annotation of devm_clk_get_optional. The annotation
says -E
On 11/2/2023 1:50 AM, Sean Anderson wrote:
> On 8/17/23 13:04, Yang Xiwen via B4 Relay wrote:
>> From: Yang Xiwen
>>
>> It's already implemented in clk-mux.c, export it in the header file.
>>
>> Signed-off-by: Yang Xiwen
>> ---
>> include/linu
On 11/2/2023 2:19 AM, Sean Anderson wrote:
> On 8/17/23 13:04, Yang Xiwen via B4 Relay wrote:
>> From: Yang Xiwen
>>
>> Calling into CCF framework will cause a clock being enabled twice
>> instead of once (clk->enable_count becomes 2 rather than 1), thus making
&
On 11/2/2023 2:01 AM, Sean Anderson wrote:
> On 11/1/23 13:55, Sean Anderson wrote:
>> On 8/17/23 13:04, Yang Xiwen via B4 Relay wrote:
>>> From: Yang Xiwen
>>>
>>> it's a very common case to register a clock without a parent, such as
>>> clk_regi
On 11/2/2023 2:50 AM, Yang Xiwen wrote:
> On 11/2/2023 2:19 AM, Sean Anderson wrote:
>> On 8/17/23 13:04, Yang Xiwen via B4 Relay wrote:
>>> From: Yang Xiwen
>>>
>>> Calling into CCF framework will cause a clock being enabled twice
>>> instead of on
Why is this patchset completely ignored for more than half a month
already? I have some other patches pending because of this one. Please
tell me what's wrong with this patchset so that i can fix them.
--
Regards,
Yang Xiwen
Also introduced a new mach-histb, should apply to hi3798cv200 and
various hi3798-series SoCs.
Yang Xiwen (4):
arm: add support for Hisilicon HiSTB family SoCs
mmc: hi6220_dw_mmc: add compatible for HC2910 support
dt-binding: histb-clock: add clocks definition for Hi3798MV200
arm: histb
First supported chip is hi3798mv200 (which is similar to Hi3798cv200
used by poplar).
Signed-off-by: Yang Xiwen
---
MAINTAINERS| 1 +
arch/arm/Kconfig | 12
arch/arm/Makefile | 1 +
arch/arm/mach-histb/Kconfig| 14
It adds compatible "hisilicon,hi3798mv200-dw-mshc" for HC2910 SoC
Hi3798MV200 to probe this mmc driver.
Signed-off-by: Yang Xiwen
---
drivers/mmc/hi6220_dw_mmc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
index
These clocks are found on Hi3798MV200
Signed-off-by: Yang Xiwen
---
include/dt-bindings/clock/histb-clock.h | 12
1 file changed, 12 insertions(+)
diff --git a/include/dt-bindings/clock/histb-clock.h
b/include/dt-bindings/clock/histb-clock.h
index 136de24733..8a05790d1a 100644
A board with Hi3798MV200 SoC and various peripherals. Details are in the
board README.md.
Signed-off-by: Yang Xiwen
---
.../hi3798mv200-hc2910-2aghd05-u-boot.dtsi| 8 +
arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts | 71 ++
arch/arm/dts/hi3798mv200-u-boot.dtsi | 22 ++
arch
On 5/3/2023 9:26 PM, Tom Rini wrote:
> On Sat, Apr 01, 2023 at 07:17:33PM +0800, Yang Xiwen wrote:
>
>> First supported chip is hi3798mv200 (which is similar to Hi3798cv200
>> used by poplar).
>>
>> Signed-off-by: Yang Xiwen
>
> For the series, applied
data = {
.clock = 5000,
.use_fifo = false,
- // FIFO depth is 256
- .fifoth_val = MSIZE(4) | RX_WMARK(0x7f) | TX_WMARK(0x80),
+ .fifo_depth = 256,
};
For HiSilicon changes in hi6220_dw_mmc.c,
Reviewed-by: Yang Xiwen
static const struct udevice_id hi
On 1/19/2024 12:24 PM, Yang Xiwen via B4 Relay wrote:
From: Yang Xiwen
This watchdog core is found on many HiSilicon SoCs. Add support for it.
Signed-off-by: Yang Xiwen
---
drivers/watchdog/Kconfig| 10 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/hisi_wdt.c | 196
/
Signed-off-by: Yang Xiwen
---
drivers/mmc/dw_mmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 400066fa99..e103664145 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -262,8 +262,8 @@ static int
On 4/3/2024 8:39 AM, Jaehoon Chung wrote:
Hi,
On 2/1/24 23:05, Yang Xiwen via B4 Relay wrote:
From: Yang Xiwen
This can avoid hardcoding a clock rate in driver. Also can enable the
clocks and deassert the resets if the pre-bootloader does not do this
for us.
Currently only enabled for
On 4/3/2024 8:41 AM, Jaehoon Chung wrote:
Hi,
On 2/1/24 23:05, Yang Xiwen via B4 Relay wrote:
From: Yang Xiwen
As described in [1], some poor hardware or cards would fail to release
the bus and keep driving data lines low. Ignore it and send the next cmd
directly seems okay for most cases
On 4/3/2024 8:43 AM, Jaehoon Chung wrote:
Hi
On 2/1/24 23:05, Yang Xiwen via B4 Relay wrote:
From: Yang Xiwen
The value defaults to 0 and is ignored by dw_mmc code, so the other
users are not affected.
Setting this explicitly fixes some weird reading error found on Hi3798MV200.
Fixes
On 2/1/2024 10:07 PM, Marek Vasut wrote:
On 2/1/24 14:16, Yang Xiwen via B4 Relay wrote:
one USB controller can have multiple ports specified in dts, all of them
should be setup to make use of all possible ports.
Is there an example of such a system ?
I'm going to send one, but no
On 2/3/2024 4:32 PM, Jorge Ramirez-Ortiz, Gmail wrote:
On 03/02/24 07:54:22, Shawn Guo wrote:
On Sat, Feb 3, 2024 at 5:44 AM Igor Opaniuk wrote:
Add myself as co-maintainer for Poplar board, as I'm currently
working on it (re-testing releases, addressing issues etc).
CC: Jorge Ramirez-Ortiz
On 2/3/2024 5:45 PM, Yang Xiwen wrote:
On 2/3/2024 4:32 PM, Jorge Ramirez-Ortiz, Gmail wrote:
On 03/02/24 07:54:22, Shawn Guo wrote:
On Sat, Feb 3, 2024 at 5:44 AM Igor Opaniuk
wrote:
Add myself as co-maintainer for Poplar board, as I'm currently
working on it (re-testing rel
On 2/3/2024 6:19 PM, Jorge Ramirez-Ortiz, Gmail wrote:
On 03/02/24 17:45:42, Yang Xiwen wrote:
On 2/3/2024 4:32 PM, Jorge Ramirez-Ortiz, Gmail wrote:
On 03/02/24 07:54:22, Shawn Guo wrote:
On Sat, Feb 3, 2024 at 5:44 AM Igor Opaniuk wrote:
Add myself as co-maintainer for Poplar board, as
On 2/5/2024 3:25 PM, Dan Carpenter wrote:
On Sat, Feb 03, 2024 at 07:01:54AM +0800, Yang Xiwen via B4 Relay wrote:
From: Yang Xiwen
clk_get_rate() return -ve on error, not 0. Fix it by replacing judging
NULL with IS_ERR_VALUE().
s/NULL/zero/.
I'd be surprised if clk_get
On 2/13/2024 12:58 AM, Tom Rini wrote:
On Tue, Feb 13, 2024 at 12:30:15AM +0800, Yang Xiwen via B4 Relay wrote:
From: Yang Xiwen
The first supported SoC is Hi3798MV200.
Signed-off-by: Yang Xiwen
---
This patchset adds support for HiSTB ioconfig module. The module is used
to set pins config
On 2/13/2024 1:08 AM, Tom Rini wrote:
On Tue, Feb 13, 2024 at 01:02:50AM +0800, Yang Xiwen wrote:
On 2/13/2024 12:58 AM, Tom Rini wrote:
On Tue, Feb 13, 2024 at 12:30:15AM +0800, Yang Xiwen via B4 Relay wrote:
From: Yang Xiwen
The first supported SoC is Hi3798MV200.
Signed-off-by: Yang
On 2/26/2024 4:23 PM, Dan Carpenter wrote:
> On Sun, Feb 25, 2024 at 08:38:33AM +0800, Yang Xiwen via B4 Relay wrote:
>> #if CONFIG_IS_ENABLED(OF_PLATDATA)
>> struct dtd_serial_pl01x *dtplat = &plat->dtplat;
>> @@ -301,10 +302,14 @@ int pl01x_serial_probe(str
On 3/11/2024 5:34 PM, Maxime Ripard wrote:
On Thu, Mar 07, 2024 at 07:18:05PM +0800, Yang Xiwen wrote:
On 3/7/2024 4:48 PM, Maxime Ripard wrote:
Hi,
On Thu, Mar 07, 2024 at 10:03:50AM +0800, Yang Xiwen via B4 Relay wrote:
From: Yang Xiwen
Originally, the initial clock rate is hardcoded to
/* get private clock struct used for cache */
clk_get_priv(clk, &clkp);
--
2.39.2
--
Regards,
Yang Xiwen
1a
change-id: 20250413-b4-qcom-wdt-e7b913fc375e
Best regards,
Thanks for your contribution. It'll be awesome if you can implement
timeout parameter support in the next version with the help of
https://pages.codelinaro.org/clo/qsdk/oss/boot/u-boot/-/blob/NHSS.QSDK.13.0.0.6/drivers/watchdog/qti_wdt.c?ref_type=heads
--
Regards,
Yang Xiwen
On 6/17/2025 12:40 AM, Neil Armstrong wrote:
On 16/06/2025 18:23, Yang Xiwen via B4 Relay wrote:
From: Yang Xiwen
meson_gpio_get() always assumes gpio is configured to input mode. This
is incorrect and breaks `gpio toggle` command:
gpio: pin aobus-banks2 (gpio 2) value is 0
Warning
On 6/4/2025 8:31 PM, Mikko Rapeli wrote:
Hi,
On Mon, Jun 02, 2025 at 12:37:10PM +0200, Quentin Schulz wrote:
+Cc Mikko Rapeli who's attempting to patch this in OpenEmbedded-Core
On 5/31/25 3:10 PM, Yang Xiwen via B4 Relay wrote:
[You don't often get email from devnull+forbidden4
On 6/2/2025 6:37 PM, Quentin Schulz wrote:
+Cc Mikko Rapeli who's attempting to patch this in OpenEmbedded-Core
On 5/31/25 3:10 PM, Yang Xiwen via B4 Relay wrote:
[You don't often get email from
devnull+forbidden405.outlook@kernel.org. Learn why this is
important at http
On 6/21/2025 6:54 PM, Yang Xiwen via B4 Relay wrote:
Currently U-Boot clk framework mandates the sequence of registering clks
to begin from root, and then its children. This is an addtional
requirement that doesn't exist in Linux kernel, which makes clk driver
porting more difficult.
On 6/21/2025 6:54 PM, Yang Xiwen via B4 Relay wrote:
Currently U-Boot clk framework mandates the sequence of registering clks
to begin from root, and then its children. This is an addtional
requirement that doesn't exist in Linux kernel, which makes clk driver
porting more difficult.
So we have to call clk_disable() twice to disable the clock.
It can be easily reproduced with few extra lines of debug code.
Fix that by calling clk->ops->enable/disable directly in
ccf_clk_endisable() rather than using the framework functions.
Signed-off-by: Yang Xiwen
---
Yang
From: Yang Xiwen
Invoking clk_enable() or clk_disable() in clk->ops context causes a
recursion, results in a clock being enabled twice.
Signed-off-by: Yang Xiwen
---
drivers/clk/clk.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk.c b/driv
From: Yang Xiwen
This allows it to be used by other source files.
Signed-off-by: Yang Xiwen
---
drivers/clk/clk-uclass.c | 5 -
include/clk.h| 17 +
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk
From: Yang Xiwen
It adds the driver for the internal MDIO bus of HIFEMAC Ethernet
controller. It's based on the mainstream linux driver.
Signed-off-by: Yang Xiwen
---
drivers/net/Kconfig| 8
drivers/net/Makefile | 1 +
drivers/net/hifemac_mdio.c
e used for Hi3798MV200 since the
clock driver is missing. I will implement and submit the clock driver
and the framework in a later patchset.
Signed-off-by: Yang Xiwen
---
Yang Xiwen (2):
net: add hifemac Ethernet driver for HiSilicon platform
net: add hifemac_mdio MDIO bus driver for
From: Yang Xiwen
It adds the driver for HIFEMAC Ethernet controller found on HiSilicon
SoCs like Hi3798MV200. It's based on the mainstream linux driver, but
quite a lot of code gets rewritten and cleaned up to adopt u-boot driver
model.
Signed-off-by: Yang Xiwen
---
drivers/net/Kc
From: Yang Xiwen
As described by the doc.
Signed-off-by: Yang Xiwen
---
Handle both ENODATA and ENOENT.
---
include/clk.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/include/clk.h b/include/clk.h
index d91285235f..c9aa2360e1 100644
--- a/include/clk.h
+++ b
From: Yang Xiwen
It adds the driver for the internal MDIO bus of HIFEMAC Ethernet
controller. It's based on the mainstream linux driver.
Signed-off-by: Yang Xiwen
---
drivers/net/Kconfig| 8
drivers/net/Makefile | 1 +
drivers/net/hifemac_mdio.c
From: Yang Xiwen
It adds the driver for HIFEMAC Ethernet controller found on HiSilicon
SoCs like Hi3798MV200. It's based on the mainstream linux driver, but
quite a lot of code gets rewritten and cleaned up to adopt u-boot driver
model.
Signed-off-by: Yang Xiwen
---
drivers/net/Kc
e used for Hi3798MV200 since the
clock driver is missing. I will implement and submit the clock driver
and the framework in a later patchset.
Signed-off-by: Yang Xiwen
---
Changes in v2:
- hisi_femac: clear previous irq before sending
- Link to v1:
https://lore.kernel.org/r/20230725-wip-hisi_fema
From: Yang Xiwen
It's already implemented in clk-mux.c, export it in the header file.
Signed-off-by: Yang Xiwen
---
include/linux/clk-provider.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index b8acacd49e..80140
They are found during my development for HiSilicon clock driver. Details
are in commit logs.
Signed-off-by: Yang Xiwen
---
Yang Xiwen (5):
clk: export clk_register_mux_table()
clk: call log_debug() instead to avoid console log printing
clk: also handle ENOENT in *_optional
From: Yang Xiwen
If the device does not specify any clocks in device tree, these
functions will return PTR_ERR(-ENOENT). This is not the intended
behavior and does not comply with linux kernel CCF. Fix that by
returning NULL under such circumstances instead.
Signed-off-by: Yang Xiwen
From: Yang Xiwen
it's a very common case to register a clock without a parent, such as
clk_register_fixed_rate(). Replace log_error() with log_debug() to avoid
useless console log if not debugging.
Signed-off-by: Yang Xiwen
---
drivers/clk/clk.c | 4 ++--
1 file changed, 2 insertions(
From: Yang Xiwen
Calling into CCF framework will cause a clock being enabled twice
instead of once (clk->enable_count becomes 2 rather than 1), thus making
it hard to disable (needs to call clk_disable() twice).
Fix that by calling clock provided ops directly.
Signed-off-by: Yang Xi
From: Yang Xiwen
So that it can be used by others.
Signed-off-by: Yang Xiwen
---
drivers/clk/clk-uclass.c | 5 -
include/linux/clk-provider.h | 5 +
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index dc3e9d6a26
From: Yang Xiwen
It adds the driver for the internal MDIO bus of HIFEMAC Ethernet
controller. It's based on the mainstream linux driver.
Signed-off-by: Yang Xiwen
---
drivers/net/Kconfig| 8
drivers/net/Makefile | 1 +
drivers/net/hifemac_mdio.c
e used for Hi3798MV200 since the
clock driver is missing. I will implement and submit the clock driver
and the framework in a later patchset.
Signed-off-by: Yang Xiwen
---
Changes in v2:
- hisi_femac: clear previous irq before sending
- Link to v1:
https://lore.kernel.org/r/20230725-wip-hisi_fema
From: Yang Xiwen
It adds the driver for HIFEMAC Ethernet controller found on HiSilicon
SoCs like Hi3798MV200. It's based on the mainstream linux driver, but
quite a lot of code gets rewritten and cleaned up to adopt u-boot driver
model.
Signed-off-by: Yang Xiwen
---
drivers/net/Kc
They are found during my development for HiSilicon clock driver. Details
are in commit logs.
Signed-off-by: Yang Xiwen
---
Yang Xiwen (5):
clk: export clk_register_mux_table()
clk: call log_debug() instead to avoid console log printing
clk: also handle ENOENT in *_optional
From: Yang Xiwen
It's already implemented in clk-mux.c, export it in the header file.
Signed-off-by: Yang Xiwen
---
include/linux/clk-provider.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index b8acacd49e..80140
From: Yang Xiwen
If the device does not specify any clocks in device tree, these
functions will return PTR_ERR(-ENOENT). This is not the intended
behavior and does not comply with linux kernel CCF. Fix that by
returning NULL under such circumstances instead.
Signed-off-by: Yang Xiwen
From: Yang Xiwen
So that it can be used by others.
Signed-off-by: Yang Xiwen
---
drivers/clk/clk-uclass.c | 5 -
include/linux/clk-provider.h | 5 +
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index dc3e9d6a26
From: Yang Xiwen
it's a very common case to register a clock without a parent, such as
clk_register_fixed_rate(). Replace log_error() with log_debug() to avoid
useless console log if not debugging.
Signed-off-by: Yang Xiwen
---
drivers/clk/clk.c | 4 ++--
1 file changed, 2 insertions(
From: Yang Xiwen
Calling into CCF framework will cause a clock being enabled twice
instead of once (clk->enable_count becomes 2 rather than 1), thus making
it hard to disable (needs to call clk_disable() twice).
Fix that by calling clock provided ops directly.
Signed-off-by: Yang Xi
From: Yang Xiwen
Assign ccf_clk_ops to .ops of clk_ccf driver so that it can act as an
clk provider. Also add "#clock-cells=<1>" to its device tree node.
Add "i2c_root" to clk_test in the device tree and driver for testing.
Get "i2c_root" clock in CCF unit
From: Yang Xiwen
assign clk_dev_ops(clkp->dev) to ops to ensure correct clk operations
are called on clocks.
This fixes the incorrect enable_count issue as described in [1].
[1]:
https://lore.kernel.org/all/sezpr06mb695927a6deeef8489a06897396...@sezpr06mb6959.apcprd06.prod.outlook.
As described in [1], enable_count is incremented by 2 when
ccf_clk_enable() is called. This series of patch fixed this issue and
added a testcase for that.
[1]:
https://lore.kernel.org/all/sezpr06mb695927a6deeef8489a06897396...@sezpr06mb6959.apcprd06.prod.outlook.com/
Signed-off-by: Yang Xiwen
From: Yang Xiwen
Fix unused variable error produced by building tests
Fixes: d3061824 (test: dm: clk_ccf: test ccf_clk_ops)
Signed-off-by: Yang Xiwen
---
it's detected by u-boot gitlab CI.
---
test/dm/clk_ccf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/te
From: Yang Xiwen
This watchdog core is found on many HiSilicon SoCs. Add support for it.
Signed-off-by: Yang Xiwen
---
drivers/watchdog/Kconfig| 10 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/hisi_wdt.c | 196
3 files changed
From: Yang Xiwen
This can avoid hardcoding a clock rate in driver. Also can enable the
clocks and deassert the resets if the pre-bootloader does not do this
for us.
Currently only enabled for Hi3798MV200.
Signed-off-by: Yang Xiwen
---
drivers/mmc/hi6220_dw_mmc.c | 61
From: Yang Xiwen
The initial commit used log_msg_ret() wrongly. Fix that by moving error
report to a separate dev_err() call and shrink the first argument of
log_msg_ret() to no more than 4 chars.
Fixes: 6b5c8d98e204 ("net: add hifemac_mdio MDIO bus driver for HiSilicon
platform")
From: Yang Xiwen
shrink the first argument of log_msg_ret(), add dev_xxx() functions for
error reporting.
Fixes: 9d8f78a2a79f7 ("net: add hifemac Ethernet driver for HiSilicon platform")
Signed-off-by: Yang Xiwen
---
drivers/net/hifem
From: Yang Xiwen
register internal MDIO bus device if it is a subnode.
Signed-off-by: Yang Xiwen
---
drivers/net/hifemac.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/net/hifemac.c b/drivers/net/hifemac.c
index 1088f3eca3..39c0233b62 100644
--- a
Fix the use of log_msg_ret() and add dev_xxx() for error reporting.
Register mdio subnode as a mdio bus device for hifemac.
Signed-off-by: Yang Xiwen
---
Yang Xiwen (3):
net: hifemac_mdio: use log_msg_ret() correctly, report error by dev_err()
net: hifemac: fix log reporting
From: Yang Xiwen
It's also valid to have #reset-cells = <2> while the third arg defaults
to ASSERT_SET.
Signed-off-by: Yang Xiwen
---
drivers/reset/reset-hisilicon.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/reset/reset-hisilicon.
From: Yang Xiwen
This function is used by HiSilicon Clock Framework.
Signed-off-by: Yang Xiwen
---
include/linux/clk-provider.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index b8acacd49e..952439ad39 100644
--- a
The first supported chip is Hi3798MV200.
Signed-off-by: Yang Xiwen
---
Yang Xiwen (2):
clk: ccf: Export clk_register_mux_table() in linux/clk-provider.h
clk: add clock framework for HiSilicon SoCs
drivers/clk/Kconfig | 7 ++
drivers/clk/Makefile
From: Yang Xiwen
Hi3798 Series SoCs have a CRG (Clock Reset Generator) module which
manages all clocks and resets of the SoC.
The first supported chip is Hi3798MV200. The unused clocks are not
registered to save space and time. Only necessary clocks are
implemented right now.
Signed-off-by
From: Yang Xiwen
This function is used by HiSilicon Clock Framework.
Signed-off-by: Yang Xiwen
---
include/linux/clk-provider.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index b8acacd49e..952439ad39 100644
--- a
The first supported chip is Hi3798MV200.
Signed-off-by: Yang Xiwen
---
Yang Xiwen (2):
clk: ccf: Export clk_register_mux_table() in linux/clk-provider.h
clk: add clock framework for HiSilicon SoCs
drivers/clk/Kconfig | 7 ++
drivers/clk/Makefile
From: Yang Xiwen
Hi3798 Series SoCs have a CRG (Clock Reset Generator) module which
manages all clocks and resets of the SoC.
The first supported chip is Hi3798MV200. The unused clocks are not
registered to save space and time. Only necessary clocks are
implemented right now.
Signed-off-by
From: Yang Xiwen
The initial commit used log_msg_ret() wrongly. Fix that by moving error
report to a separate dev_err() call and shrink the first argument of
log_msg_ret() to no more than 4 chars.
Fixes: 6b5c8d98e204 ("net: add hifemac_mdio MDIO bus driver for HiSilicon
platform")
From: Yang Xiwen
shrink the first argument of log_msg_ret(), add dev_xxx() functions for
error reporting.
Fixes: 9d8f78a2a79f7 ("net: add hifemac Ethernet driver for HiSilicon platform")
Signed-off-by: Yang Xiwen
---
drivers/net/hifem
From: Yang Xiwen
register internal MDIO bus device if it is a subnode.
Signed-off-by: Yang Xiwen
---
drivers/net/hifemac.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/net/hifemac.c b/drivers/net/hifemac.c
index 1088f3eca3..39c0233b62 100644
--- a
From: Yang Xiwen
3 operations needed by `net stats` are implemented. New `net stats`
output some useful info.
Signed-off-by: Yang Xiwen
---
drivers/net/hifemac.c | 87 +++
1 file changed, 87 insertions(+)
diff --git a/drivers/net/hifemac.c b
Fix the use of log_msg_ret() and add dev_xxx() for error reporting.
Register mdio subnode as a mdio bus device for hifemac.
Implement ops needed by `net stats`
Signed-off-by: Yang Xiwen
---
Changes in v2:
- hisi-femac: add statistics related operations
- Link to v1:
https://lore.kernel.org/r
From: Yang Xiwen
They are not required to be global, make them static.
Signed-off-by: Yang Xiwen
---
drivers/net/hifemac.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/hifemac.c b/drivers/net/hifemac.c
index d24023eefd..90cc247b3b 100644
--- a/drivers
- Fix the use of log_msg_ret() and add dev_xxx() for error reporting.
- Register mdio subnode as a mdio bus device for hifemac.
- Implement ops needed by `net stats`
- Make functions static.
Signed-off-by: Yang Xiwen
---
Changes in v3:
- hisi-femac: add missing `static` to avoid polluting global
From: Yang Xiwen
shrink the first argument of log_msg_ret(), add dev_xxx() functions for
error reporting.
Fixes: 9d8f78a2a79f7 ("net: add hifemac Ethernet driver for HiSilicon platform")
Signed-off-by: Yang Xiwen
---
drivers/net/hifem
From: Yang Xiwen
register internal MDIO bus device if it is a subnode.
Signed-off-by: Yang Xiwen
---
drivers/net/hifemac.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/net/hifemac.c b/drivers/net/hifemac.c
index 1088f3eca3..39c0233b62 100644
--- a
From: Yang Xiwen
The initial commit used log_msg_ret() wrongly. Fix that by moving error
report to a separate dev_err() call and shrink the first argument of
log_msg_ret() to no more than 4 chars.
Fixes: 6b5c8d98e204 ("net: add hifemac_mdio MDIO bus driver for HiSilicon
platform")
From: Yang Xiwen
3 operations needed by `net stats` are implemented. New `net stats`
output some useful info.
Signed-off-by: Yang Xiwen
---
drivers/net/hifemac.c | 87 +++
1 file changed, 87 insertions(+)
diff --git a/drivers/net/hifemac.c b
From: Yang Xiwen
It is found that when DM is enabled, only generic init function is
called in .probe(). Baudrate is never honored. Add a function call
to .setbrg() when probing so that we can update the baudrate of the
serial device.
Signed-off-by: Yang Xiwen
---
drivers/serial/serial_pl01x.c
From: Yang Xiwen
For some gate clocks and fixed clocks without a parent, calling
clk_register will print an useless error message indicating that parent
is missing. Fix that by gaurding log_xxx() with an if-statement.
Signed-off-by: Yang Xiwen
Suggested-by: Sean Anderson
---
It's found d
From: Yang Xiwen
This clock is added to dts. Get it in the devm group in the driver or
the testcases will fail.
Signed-off-by: Yang Xiwen
---
arch/sandbox/dts/test.dts | 5 +++--
arch/sandbox/include/asm/clk.h | 1 +
drivers/clk/clk_sandbox_test.c | 5 +
3 files changed, 9 insertions
From: Yang Xiwen
assign clk_dev_ops(clkp->dev) to ops to ensure correct clk operations
are called on clocks.
This fixes the incorrect enable_count issue as described in [1].
[1]:
https://lore.kernel.org/all/sezpr06mb695927a6deeef8489a06897396...@sezpr06mb6959.apcprd06.prod.outlook.
As described in [1], enable_count is incremented by 2 when
ccf_clk_enable() is called. This series of patch fixed this issue and
added a testcase for that.
[1]:
https://lore.kernel.org/all/sezpr06mb695927a6deeef8489a06897396...@sezpr06mb6959.apcprd06.prod.outlook.com/
Signed-off-by: Yang Xiwen
From: Yang Xiwen
get i2c_root clock from device tree. In this way we get an CCF clock and
also test ccf_clk_ops.
Signed-off-by: Yang Xiwen
---
test/dm/clk_ccf.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c
index
From: Yang Xiwen
It can now act as an clk provider on which ccf_clk_ops can be tested.
Also add "#clock-cells=<1>" to test.dts.
---
arch/sandbox/dts/test.dts | 1 +
drivers/clk/clk_sandbox_ccf.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/sandbox/dts/test.dt
From: Yang Xiwen
get i2c_root clock from device tree. In this way we get an CCF clock and
also test ccf_clk_ops.
Signed-off-by: Yang Xiwen
---
test/dm/clk_ccf.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c
index
As described in [1], enable_count is incremented by 2 when
ccf_clk_enable() is called. This series of patch fixed this issue and
added a testcase for that.
[1]:
https://lore.kernel.org/all/sezpr06mb695927a6deeef8489a06897396...@sezpr06mb6959.apcprd06.prod.outlook.com/
Signed-off-by: Yang Xiwen
From: Yang Xiwen
This clock is added to dts. Get it in the devm group in the driver or
the testcases will fail.
Signed-off-by: Yang Xiwen
---
arch/sandbox/dts/test.dts | 5 +++--
arch/sandbox/include/asm/clk.h | 1 +
drivers/clk/clk_sandbox_test.c | 5 +
3 files changed, 9 insertions
From: Yang Xiwen
It can now act as an clk provider on which ccf_clk_ops can be tested.
Also add "#clock-cells=<1>" to test.dts.
Signed-off-by: Yang Xiwen
---
arch/sandbox/dts/test.dts | 1 +
drivers/clk/clk_sandbox_ccf.c | 1 +
2 files changed, 2 insertions(+)
diff --gi
From: Yang Xiwen
assign clk_dev_ops(clkp->dev) to ops to ensure correct clk operations
are called on clocks.
This fixes the incorrect enable_count issue as described in [1].
[1]:
https://lore.kernel.org/all/sezpr06mb695927a6deeef8489a06897396...@sezpr06mb6959.apcprd06.prod.outlook.
one USB controller can have multiple ports specified in dts, all of them
should be setup to make use of all possible ports.
Signed-off-by: Yang Xiwen
---
Yang Xiwen (3):
phy: add generic_setup(shutdown)_phy_bulk()
test: phy: test generic_setup(shutdown)_phy_bulk()
usb: ehci
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