spl-dtb.hex" is needed to
generate the final configuration bitstream for Intel SOCFPGA SOC64
devices.
Signed-off-by: Dalon Westergreen
Signed-off-by: Siew Chin Lim
---
v4:
- Replace CONFIG_TARGET_SOCFPGA_STRATIX10/AGILEX with
CONFIG_TARGET_SOCFPGA_SOC64.
- Add this patch into 'VAB
f-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index c90f63a754..0b0eb7a259 100644
-
f-by: Siew Chin Lim
---
v2: Mark boot_scratch_cold3 as reserved for customer use.
---
arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/Kconfig| 6 +++---
arch/arm/mach-socfpga/Kconfig | 5 +
arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +--
arch
on:
Enable ARM Trusted Firmware for U-Boot
https://lists.denx.de/pipermail/u-boot/2020-August/423530.html
[1]:
https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html
Siew Chin Lim (22):
arm: socfpga: Move Stratix10 and Agilex to use
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 5 +++--
.../mach-socfpga/{system_manager_s10.c => system_manager_soc64.c}| 0
2 files changed
Disable the MPFE firewall for SMMU and HMC adapter for
Agilex and Diamond Mesa.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/firewall.c | 10 ++
arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 1 +
arch/arm/mach-socfpga/include/mach/firewall.h | 6
Reuse base_addr_s10.h for Diamond Mesa, the address is the
same as Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
b/arch/arm/mach
Rename to common file name to used by all SOC64 devices.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile| 4 ++--
.../mach-socfpga/{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} | 2 +-
2 files changed, 3 insertions(+), 3 deleti
No functionality change. In preparation for Stratix10 and
Agilex handoff function restructuring.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 46 +++---
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-socfpga
Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from
S10_HANDOFF to SOC64_HANDOFF.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/clock_manager_s10.c | 2 +-
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39 --
arch/arm/mach-socfpga
Diamond Mesa support both HPS handoff data and DDR handoff data.
HPS handoff data support re-use Straix10 and Agilex code. DDR
handoff data is newly introduced in Diamond Mesa.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 19 ++
arch/arm/mach
Add Diamond Mesa clock manager to socfpga_get_managers_addr
function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ac2b891fad..b63eec779a 100644
--- a/arch
handoff
function in wrap_handoff_soc64.c.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 +-
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 21 +++
.../include/mach/system_manager_soc64.h| 4 --
arch/arm/mach-socfpga
Add clock manager driver for Diamond Mesa. Provides clock
initialization and get_rate functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-dm.c | 504 +++
drivers/clk/altera/clk-dm.h
limited bits, QSPI reference clock frequency is
converted to kHz from Hz.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/clock_manager.c | 5 ++--
.../include/mach/system_manager_soc64.h| 12 +-
arch/arm/mach-socfpga
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/clock_manager.c | 10 ++
arch/arm/mach-socfpga/clock_manager_agilex.c | 6 --
arch/arm/mach
Add memory clock manager driver for Diamond Mesa. Provides
clock initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 2 +-
drivers/clk/altera/clk-mem-dm.c | 135
drivers/clk/altera/clk-mem-dm.h | 80
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/clock_manager_dm.c | 79 ++
arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 +
.../mach-socfpga/include/mach/clock_manager_dm.h | 14
3 files changed, 95 insertions(+)
create mode 100644 arch/arm
Move Stratix10 and Agilex SPL common code to spl_soc64.c
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 2 ++
arch/arm/mach-socfpga/spl_agilex.c | 16
arch/arm/mach-socfpga/spl_s10.c| 17 -
arch/arm/mach-socfpga/spl_soc64.c | 26
DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/firewall.h |1 +
.../include/mach/system_manager_soc64.h
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/spl_dm.c | 93 ++
1 file changed, 93 insertions(+)
create mode 100644 arch/arm/mach-socfpga/spl_dm.c
diff --git a/arch/arm/mach-socfpga/spl_dm.c b/arch/arm/mach-socfpga/spl_dm.c
new file mode 100644
Signed-off-by: Siew Chin Lim
---
board/intel/dm-socdk/MAINTAINERS | 7 +++
board/intel/dm-socdk/Makefile| 7 +++
board/intel/dm-socdk/socfpga.c | 7 +++
3 files changed, 21 insertions(+)
create mode 100644 board/intel/dm-socdk/MAINTAINERS
create mode 100644 board/intel/dm
Add defconfig for Diamond Mesa to support both
legacy boot flow and ATF boot flow.
Legacy boot:
SPL -> U-Boot proper -> OS (Linux)
ATF boot flow:
SPL -> ATF(BL31) -> U-Boot proper -> OS (Linux)
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig| 18 ++
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_dm-u-boot.dtsi | 100 +
arch/arm/dts/socfpga_dm.dtsi | 640 ++
arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_dm_socdk.h | 46 ++
1 file changed, 46 insertions(+)
create mode 100644 include/configs/socfpga_dm_socdk.h
diff --git a/include/configs/socfpga_dm_socdk.h
b/include/configs/socfpga_dm_socdk.h
new file
From: Chee Hong Ang
CONFIG_OF_EMBED was primarily enabled to support the S10/Agilex
spl hex file requirements. Since this option now produces a
warning during build, and the spl hex can be created using
alternate methods, CONFIG_OF_EMBED is no longer needed.
Signed-off-by: Chee Hong Ang
---
c
This is the 2nd version of patchset to Enable ARM Trusted Firmware
for U-Boot.
New U-boot flow with ARM Trusted Firmware (ATF) support:
SPL (EL3) -> ATF-BL31 (EL3) -> U-Boot Proper (EL2) -> Linux (EL1)
SPL loads the u-boot.itb which consist of:
1) u-boot-nodtb.bin (U-Boot Proper image)
2) u-boot.
From: Chee Hong Ang
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do no
From: Chee Hong Ang
Override 'lowlevel_init' to make sure secondary CPUs trapped
in ATF instead of SPL. After ATF is initialized, it will signal
the secondary CPUs to jump from SPL to ATF waiting to be 'activated'
by Linux OS via PSCI call.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpg
From: Chee Hong Ang
Instead of loading u-boot proper image (u-boot.img), SPL
now loads FIT image (u-boot.itb) which includes u-boot
proper, ATF and u-boot proper's DTB.
Signed-off-by: Chee Hong Ang
---
include/configs/socfpga_soc64_common.h | 4
1 file changed, 4 insertions(+)
diff --git
From: Chee Hong Ang
Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable SMP
booting in Linux on SoC 64bits platform.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Kconfig | 2 --
1 file changed, 2 deletions(-)
diff --gi
From: Chee Hong Ang
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
v2:
- Code clean up without functionality change:
- Changed socfpga_dwmci_fw_clksel
From: Chee Hong Ang
invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.
smc_send_mailbox() is a send mailbox co
From: Chee Hong Ang
Generate a FIT image for Intel SOCFPGA (64bits) which
include U-boot proper, ATF and DTB for U-boot proper.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
v2:
- Move soc64 folder from board/altera to board/intel folder
---
board/intel/soc64/fit_spl_atf.sh
sters access, 2nd phase bitstream FPGA reconfiguration, Remote
System Update (RSU) and etc.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
v2:
- Updated comments:
- Changed string 'kernel tree' to 'u-boot tree'
- INTEL_SIP_SMC_STATUS_OK and INTEL_SIP_SMC
From: Chee Hong Ang
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
v2:
- Code clean up without functionality change:
- Changed dwmac_socfpga_fw_setphy() to
From: Chee Hong Ang
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
v2:
- Print error message and return instead of hang in
socfpga_bridges_reset
From: Chee Hong Ang
Since SSBL is running in DRAM, it shall setup the stack in DRAM
instead of OCRAM which is occupied by SPL and handoff data.
Signed-off-by: Chee Hong Ang
---
include/configs/socfpga_soc64_common.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/socfp
From: Chee Hong Ang
SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 ++-
1 file chang
TEXT_BASE).
ATF will occupy the address range starting from 0x1000.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
v2:
- Add CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
- Move board/altera/soc64/fit_spl_atf.sh to
board/intel/soc64/fit_spl_atf.sh
---
configs/socfpga_agilex_atf_defconfi
From: Chee Hong Ang
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga
From: Chee Hong Ang
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/intel_sdm_mb.c | 139
1 file changed, 139 insertions(+)
diff
From: Chee Hong Ang
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do no
From: Chee Hong Ang
Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable SMP
booting in Linux on SoC 64bits platform.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Kconfig | 2 --
1 file changed, 2 deletions(-)
diff --gi
ocfpga: soc64: Skip handoff data access in SSBL
configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
support
Siew Chin Lim (2):
arm: socfpga: dts: soc64: Add binman node of FIT image with ATF
support
arm: socfpga: soc64: Enable FIT image generation using binman
Makefil
From: Chee Hong Ang
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/reset_manager_s10.c | 13 +
1 file changed, 13
From: Chee Hong Ang
invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.
smc_send_mailbox() is a send mailbox co
From: Chee Hong Ang
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/intel_sdm_mb.c | 139
1 file changed, 139 insertions(+)
diff
From: Chee Hong Ang
Since SSBL is running in DRAM, it shall setup the stack in DRAM
instead of OCRAM which is occupied by SPL and handoff data.
Signed-off-by: Chee Hong Ang
---
include/configs/socfpga_soc64_common.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/socfp
From: Chee Hong Ang
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
drivers/mmc/socfpga_dw_mmc.c | 17 +
1 file changed, 17 insertions(+)
e Hong Ang
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_soc64_common.h | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index fb5e2e8aaf..990f879b07 100644
--- a/inclu
From: Chee Hong Ang
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga
sters access, 2nd phase bitstream FPGA reconfiguration, Remote
System Update (RSU) and etc.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
include/linux/intel-smc.h | 573 ++
1 file changed, 573 insertions(+)
create mode 100644 include/
From: Chee Hong Ang
Override 'lowlevel_init' to make sure secondary CPUs trapped
in ATF instead of SPL. After ATF is initialized, it will signal
the secondary CPUs to jump from SPL to ATF waiting to be 'activated'
by Linux OS via PSCI call.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpg
TEXT_BASE).
ATF will occupy the address range starting from 0x1000.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
configs/socfpga_agilex_atf_defconfig| 72
configs/socfpga_stratix10_atf_defconfig | 74 +
2 files cha
From: Chee Hong Ang
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
drivers/net/dwmac_socfpga.c | 30 ++
1 file changed, 26 insertions(+), 4
From: Chee Hong Ang
SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 ++-
1 file chang
boot with and without VAB
feature, we skip binman for ARCH_SOCFPGA in default Makefile
flow. User always use 'make fit-itb' to generate FIT image
after successfully compile u-boot.
Signed-off-by: Siew Chin Lim
---
Makefile | 7 +++
arch/arm/mach-socfpga/Kco
Add binman node to device tree to generate the FIT image for u-boot
(u-boot.itb) and OS kernel (kernel.itb).
u-boot.itb contains arm trusted firmware (ATF), u-boot proper and
u-boot device tree for ATF u-boot flow.
kernel.itb contains Linux Image and Linux device tree.
Signed-off-by: Siew Chin
org/project/uboot/cover/20210712094921.16950-1-elly.siew.chin@intel.com/
Siew Chin Lim (14):
arm: socfpga: Move linux_qspi_enable from bootcommand to
board_prep_linux function
arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
arm: socfpga: Add base address for Intel N5X dev
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim
---
.../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8
include/configs/socfpga_soc64_common.h
d 'linux_qspi_enable' will refer to 'fdt_addr'
environment value to retrieve the device tree node.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/board.c | 17 +
configs/socfpga_agilex_atf_defconfig| 2 +-
configs/socfpga_stratix10_at
Reuse base_addr_soc64.h for Intel N5X device, the address is the
same as Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
b
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-n5x.c | 489 ++
drivers/clk/altera/clk-n5x.h | 217
From: Tien Fong Chee
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index f8d3d48ee8..9c19157de7 100644
--- a/arch/arm/mach
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-mem-n5x.c | 136 +++
drivers/clk/altera/clk-mem-n5x.h | 84
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...{clock_manager_agilex.c => clock_manager_n5x.c} | 32 ++
arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 ++
.../mach-socfpga/include/mach/clock_manager_n5x.h | 12
3 files changed,
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
drivers/ddr/altera/sdram_soc64.c | 24 +---
1 fi
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deleti
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 ++-
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agile
calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
.../include/mach
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files chan
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v5:
- Sort the node name in alphanumeric order in socfpga_n5x_socdk-u-boot.dtsi
- Remove duplicated qspi node from socfpga_n5x_socdk-u-boot.dtsi,
It is defined in socfpga_n5x_socdk.dtsi
v4:
- Reuse
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig | 21 +++-
arch/arm/mach-socfpga/Makefile | 28 ++
...lex_vab_defconfig
868-1-elly.siew.chin@intel.com/
[v4]
https://patchwork.ozlabs.org/project/uboot/cover/20210712094921.16950-1-elly.siew.chin@intel.com/
[v5]
https://patchwork.ozlabs.org/project/uboot/cover/20210809071841.187051-1-elly.siew.chin@intel.com/
Siew Chin Lim (14):
arm: socfpga: M
d 'linux_qspi_enable' will refer to 'fdt_addr'
environment value to retrieve the device tree node.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/board.c | 17 +
configs/socfpga_agilex_atf_defconfig| 2 +-
configs/socfpga_stratix10_at
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim
---
.../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8
include/configs/socfpga_soc64_common.h
Reuse base_addr_soc64.h for Intel N5X device, the address is the
same as Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
b
From: Tien Fong Chee
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-n5x.c | 489 ++
drivers/clk/altera/clk-n5x.h | 217
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index f8d3d48ee8..9c19157de7 100644
--- a/arch/arm/mach
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-mem-n5x.c | 136 +++
drivers/clk/altera/clk-mem-n5x.h | 84
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...{clock_manager_agilex.c => clock_manager_n5x.c} | 32 ++
arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 ++
.../mach-socfpga/include/mach/clock_manager_n5x.h | 12
3 files changed,
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deleti
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
drivers/ddr/altera/sdram_soc64.c | 24 +---
1 fi
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 ++-
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agile
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files chan
calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
.../include/mach
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v6:
- Sort the node name in alphanumeric order in socfpga_n5x_socdk-u-boot.dtsi
- Remove duplicated qspi node from socfpga_n5x_socdk-u-boot.dtsi,
It is defined in socfpga_n5x_socdk.dtsi
- Remove the
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig | 21 +++-
arch/arm/mach-socfpga/Makefile | 28 ++
...lex_vab_defconfig
iver
arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to
mbox_reset_cold()
arm: socfpga: soc64: SSBL shall not setup stack on OCRAM
arm: socfpga: soc64: Skip handoff data access in SSBL
configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF
support
Siew Chin L
From: Chee Hong Ang
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do no
e Hong Ang
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_soc64_common.h | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index fb5e2e8aaf..990f879b07 100644
--- a/inclu
From: Chee Hong Ang
Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable SMP
booting in Linux on SoC 64bits platform.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Kconfig | 2 --
1 file changed, 2 deletions(-)
diff --gi
201 - 300 of 366 matches
Mail list logo
