handoff
function in wrap_handoff_soc64.c.
Signed-off-by: Siew Chin Lim
---
v2
- Change "#ifdef" to "#if IS_ENABLED()"
- Change to use captial letter for enum macros (LITTLE_ENDIAN, BIG_ENDIAN)
- Soft include files by alphabetical order in system_manager_soc64.c
and wrap_handof
work.ozlabs.org/project/uboot/patch/20210315075916.26336-1-elly.siew.chin@intel.com/
2. Restructure Stratix10 and Agilex handoff code
https://patchwork.ozlabs.org/project/uboot/cover/20210315094329.30282-1-elly.siew.chin....@intel.com/
Siew Chin Lim (2):
arm: socfpga: Move Str
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/clock_manager.c | 15 ---
arch/arm/mach-socfpga/clock_manager_agilex.c | 6 --
arch/arm
bits, QSPI reference clock frequency is
converted to kHz from Hz.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v2:
- Rename mbox_qspi_set_controller_clk_hz function to
cm_set_qspi_controller_clk_hz function and move to clock_manager.c.
- Remove CLOCK_1K macro from
.30282-1-elly.siew.chin....@intel.com/
Siew Chin Lim (2):
arm: socfpga: Move Stratix10 and Agilex clock manager common code
arm: socfpga: Changed to store QSPI reference clock in kHz
arch/arm/mach-socfpga/clock_manager.c | 43 --
arch/arm/mach-socfpga/clock_mana
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v3:
- Declare cm_get_qspi_controller_clk_hz function in clock_manager.h
to share by all Intel SOCFPGA.
- Remove cm_get_qspi_controller_clk_hz function
bits, QSPI reference clock frequency is
converted to kHz from Hz.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v2:
- Rename mbox_qspi_set_controller_clk_hz function to
cm_set_qspi_controller_clk_hz function and move to clock_manager.c.
- Remove CLOCK_1K macro from
Add signature with crc32 value for all images in binman node for FIT
image in device tree. And, enable FIT signature checking for Stratix10
and Agilex ATF and VAB sdmmc boot.
Signed-off-by: Siew Chin Lim
---
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 30 +-
configs
Add function to send mailbox command via SMC to get usercode from SDM.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/smc_api.h | 1 +
arch/arm/mach-socfpga/smc_api.c | 17 +
include/linux/intel-smc.h| 18
, and ATF boot
with VAB enabled.
[1]:
https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html
Siew Chin Lim (16):
arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
arm: socfpga: Add base address for Intel N5X device
arm: socfpga
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim
---
.../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8
include/configs/socfpga_soc64_common.h
Reuse base_addr_soc64.h for Intel N5X device, the address is the
same as Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
b
N5X support both HPS handoff data and DDR handoff data.
HPS handoff data support re-use Straix10 and Agilex code. DDR
handoff data is newly introduced for N5X.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 28 +++
arch/arm/mach-socfpga
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 64a7c9d652..9305bec38a 100644
--- a/arch/arm/mach
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-n5x.c | 489 ++
drivers/clk/altera/clk-n5x.h | 217
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-mem-n5x.c | 136 +++
drivers/clk/altera/clk-mem-n5x.h | 84
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deleti
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...{clock_manager_agilex.c => clock_manager_n5x.c} | 32 ++
arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 ++
.../mach-socfpga/include/mach/clock_manager_n5x.h | 12
3 files changed,
Add is_ddr_init_skipped function to check if need to skip DDR
initialization for N5X. This patch is preparation for N5X DDR
driver support.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/misc.h | 4 ++
arch/arm/mach-socfpga/misc_soc64.c
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
drivers/ddr/altera/sdram_soc64.c | 18 --
1 file cha
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 ++-
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agile
DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
.../include/mach/system_manager_soc64.h
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files chan
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/dts/Makefile | 1 +
..._agilex-u-boot.dtsi => socfpga_n5x-u-boot.dtsi} | 13 ++--
.../dts/{socfpga_agilex.dtsi => socfpga_n5x.dtsi} | 90 +-
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig | 20 +++-
arch/arm/mach-socfpga/Makefile | 22 +-
...lex_atf_defconfig
sed parameter "u-boot,boot0"
History:
[v1]
https://patchwork.ozlabs.org/project/uboot/cover/20210331143908.48211-1-elly.siew.chin@intel.com/
[v2]
https://patchwork.ozlabs.org/project/uboot/cover/20210430073814.193576-1-elly.siew.chin@intel.com/
Siew Chin Lim (14):
arm:
d 'linux_qspi_enable' will refer to 'fdt_addr'
environment value to retrieve the device tree node.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/board.c | 17 +
configs/socfpga_agilex_atf_defconfig| 2 +-
configs/socfpga_stratix10_at
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim
---
.../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8
include/configs/socfpga_soc64_common.h
Reuse base_addr_soc64.h for Intel N5X device, the address is the
same as Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
b
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 64a7c9d652..9305bec38a 100644
--- a/arch/arm/mach
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim
---
v3:
- Use BIT() macro for CLKMGR_INTER_*_MASK macro
v2:
- common.h need to be included before clock_manager.h
- Remove unnecessary comment : write 1 to clear
- Remove
From: Tien Fong Chee
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v3
- Adding helper function for getting endianness type
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
v3:
- Use BIT() and GENMASK() macro for all *MASK macro
v2:
- common.h need to be included before clock_manager.h
- For consistency, use small letter fo 0x0c and
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deleti
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...k_manager_agilex.c => clock_manager_n5x.c} | 32 +--
.../mach-socfpga/include/mach/clock_manager.h | 2 ++
.../include/mach/clock_manager_n5x.h | 12 +++
3 files changed, 29 insertions(+), 17 deleti
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
drivers/ddr/altera/sdram_soc64.c | 24 +---
1 fi
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
.../mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 +++
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/ar
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
.../{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files changed, 9 inse
calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v3:
- Sorting header
- Used prefix OPM_xxx
- Simplify the code with do...while loop
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v3:
- Update comment for memory example code
- Move all common dts settings for N5X from
socfpga_n5x_socdk.dts to socfpga_n5x-u-boot.dtsi
- Remove unused parameter "u-boot,boot0"
v2
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig | 21 +-
arch/arm/mach-socfpga/Makefile| 28 +++
...ab_defconfig => socfpga_n5x_atf_defconfig} |
1110070505.26935-1-elly.siew.chin@intel.com/
[v2]:
https://patchwork.ozlabs.org/project/uboot/cover/20210107100337.45293-1-elly.siew.chin@intel.com/
Siew Chin Lim (6):
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
arm: socfpga: soc64: Support Vendor Authorized Boot (
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/Kconfig| 6 +++---
arch/arm/mach-socfpga/Kconfig | 5 +
arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +--
arch
Secure Device Manager (SDM)
for authentication. U-Boot will validate the SHA384 of the image
against the SHA384 hash stored in the VAB certificate before
sending the image to SDM for authentication.
Signed-off-by: Siew Chin Lim
---
v3
---
- Add description for function 'socfpga_vendor_authentic
Support 'vab' command to perform vendor authentication.
Command format: vab addr len
Authorize 'len' bytes starting at 'addr' via vendor public key
Signed-off-by: Siew Chin Lim
---
v3
---
- Remove the print in 'vab' command to avoid duplicated print
FIT image of Vendor Authentication Coot (VAB) contains signed images.
Signed-off-by: Siew Chin Lim
---
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
b/arch/arm/dts
CONFIG_BOOTCOMMAND have been moved to Kconfig.boot. This patch
move the CONFIG_BOOTCOMMAND macro from socfpga_soc64_common.h to
*_defconfig file for both Stratix 10 and Agilex.
Signed-off-by: Siew Chin Lim
---
configs/socfpga_agilex_atf_defconfig| 2 ++
configs/socfpga_agilex_defconfig
Booting Agilex with Vendor Authorized Boot.
Signed-off-by: Siew Chin Lim
---
.../{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}| 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
copy configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}
(92%)
8-1-elly.siew.chin@intel.com/
Siew Chin Lim (14):
arm: socfpga: Move linux_qspi_enable from bootcommand to
board_prep_linux function
arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
arm: socfpga: Add base address for Intel N5X device
drivers: clk: Add clock driver for Intel N5X dev
d 'linux_qspi_enable' will refer to 'fdt_addr'
environment value to retrieve the device tree node.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/board.c | 17 +
configs/socfpga_agilex_atf_defconfig| 2 +-
configs/socfpga_stratix10_at
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim
---
.../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8
include/configs/socfpga_soc64_common.h
Reuse base_addr_soc64.h for Intel N5X device, the address is the
same as Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
b
From: Tien Fong Chee
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-n5x.c | 489 ++
drivers/clk/altera/clk-n5x.h | 217
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 64a7c9d652..9305bec38a 100644
--- a/arch/arm/mach
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-mem-n5x.c | 136 +++
drivers/clk/altera/clk-mem-n5x.h | 84
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deleti
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...{clock_manager_agilex.c => clock_manager_n5x.c} | 32 ++
arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 ++
.../mach-socfpga/include/mach/clock_manager_n5x.h | 12
3 files changed,
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
drivers/ddr/altera/sdram_soc64.c | 24 +---
1 fi
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 ++-
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agile
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files chan
calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
.../include/mach
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v4:
- Reuse socfpga_n5x_socdk.dts from Linux and add U-boot specifc dts
to u-boot.dtsi. Linux socfpga_n5x_socdk.dts:
https://github.com/altera-opensource/linux-socfpga/blob/socfpga-5.4.114-lts/arch
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig | 21 +++-
arch/arm/mach-socfpga/Makefile | 28 ++
...lex_vab_defconfig
smc and hvc commands take upto 8 user input arguments, the maximum
number of arguments of the U_BOOT_CMD macro should set to 9.
Besides, fix the typo (arg7 -> arg6) in hvc command's help message.
Signed-off-by: Siew Chin Lim
---
cmd/smccc.c | 6 +++---
1 file changed, 3 insertio
Signed-off-by: Siew Chin Lim
---
arch/arm/include/asm/secure.h | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index 64e5582c1f..63a21f89ce 100644
--- a/arch/arm/include/asm/secure.h
+++
Include "compiler.h" in sha512.c. This is needed by 'cpu_to_be64' macro
that used in 'sha512_base_do_finalize' function.
Signed-off-by: Siew Chin Lim
---
lib/sha512.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/lib/sha512.c b/lib/sha512.c
index f1e2acf0f
From: Dalon Westergreen
Some architectures, Stratix10/Agilex, require a hex formatted spl that
combines the spl image and dtb. This adds a target to create said hex
file with and offset of SPL_TEXT_BASE.
Signed-off-by: Dalon Westergreen
Signed-off-by: Siew Chin Lim
---
Makefile
Signed-off-by: Siew Chin Lim
---
v2 : Update "asm\global_data.h" to "asm/global_data.h" in commit message.
---
---
arch/arm/include/asm/secure.h | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/arch/arm/include/asm/secure.h b/arch/
Commit "common: Drop asm/global_data.h from common header" added
asm/global_data.h into secure.h. However, secure.h will be included
by psci.S. Adding asm/global_data.h has caused compilation failure in
pcsi.S. Add "ifndef __ASSEMBLY__" in asm/global_data.h.
Signed-o
spl-dtb.hex" is needed to generate the final configuration bitstream
for Intel SOCFPGA SOC64 devices.
Signed-off-by: Dalon Westergreen
Signed-off-by: Siew Chin Lim
---
v2: Update commit message
---
---
Makefile | 11 ++-
include/configs/socfpga_soc64_common.h
or combined spl
and dtb
Siew Chin Lim (6):
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
arm: socfpga: cmd: Support 'vab' command
arm: socfpga: dts: soc64: Update filename in binman node of FIT im
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/Kconfig| 6 +++---
arch/arm/mach-socfpga/Kconfig | 5 +
arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +--
arch
Secure Device Manager (SDM)
for authentication. U-Boot will validate the SHA384 of the image
against the SHA384 hash stored in the VAB certificate before
sending the image to SDM for authentication.
Signed-off-by: Siew Chin Lim
---
v4:
- Move function 'board_fit_image_post_process
Support 'vab' command to perform vendor authentication.
Command format: vab addr len
Authorize 'len' bytes starting at 'addr' via vendor public key
Signed-off-by: Siew Chin Lim
---
v3
---
- Remove the print in 'vab' command to avoid duplicated print
FIT image of Vendor Authentication Coot (VAB) contains signed images.
Signed-off-by: Siew Chin Lim
---
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
b/arch/arm/dts
CONFIG_BOOTCOMMAND have been moved to Kconfig.boot. This patch
move the CONFIG_BOOTCOMMAND macro from socfpga_soc64_common.h to
*_defconfig file for both Stratix 10 and Agilex.
Signed-off-by: Siew Chin Lim
---
configs/socfpga_agilex_atf_defconfig| 2 ++
configs/socfpga_agilex_defconfig
Booting Agilex with Vendor Authorized Boot.
Signed-off-by: Siew Chin Lim
---
.../{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}| 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
copy configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}
(92%)
spl-dtb.hex" is needed to generate the final configuration bitstream
for Intel SOCFPGA SOC64 devices.
Signed-off-by: Dalon Westergreen
Signed-off-by: Siew Chin Lim
---
v4
---
- Replace CONFIG_TARGET_SOCFPGA_STRATIX10/AGILEX with
CONFIG_TARGET_SOCFPGA_SOC64.
- Add this patch into 'VAB
or combined spl
and dtb
Siew Chin Lim (6):
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
arm: socfpga: cmd: Support 'vab' command
arm: socfpga: dts: soc64: Update filename in binman node of FIT im
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/Kconfig| 6 +++---
arch/arm/mach-socfpga/Kconfig | 5 +
arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +--
arch
Secure Device Manager (SDM)
for authentication. U-Boot will validate the SHA384 of the image
against the SHA384 hash stored in the VAB certificate before
sending the image to SDM for authentication.
Signed-off-by: Siew Chin Lim
---
v4:
- Move function 'board_fit_image_post_process
Support 'vab' command to perform vendor authentication.
Command format: vab addr len
Authorize 'len' bytes starting at 'addr' via vendor public key
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/vab.c| 34 +++
FIT image of Vendor Authentication Coot (VAB) contains signed images.
Signed-off-by: Siew Chin Lim
---
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
b/arch/arm/dts
CONFIG_BOOTCOMMAND have been moved to Kconfig.boot. This patch
move the CONFIG_BOOTCOMMAND macro from socfpga_soc64_common.h to
*_defconfig file for both Stratix 10 and Agilex.
Signed-off-by: Siew Chin Lim
---
configs/socfpga_agilex_atf_defconfig| 2 ++
configs/socfpga_agilex_defconfig
Booting Agilex with Vendor Authorized Boot.
Signed-off-by: Siew Chin Lim
---
.../{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}| 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
copy configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}
(92%)
spl-dtb.hex" is needed to
generate the final configuration bitstream for Intel SOCFPGA SOC64
devices.
Signed-off-by: Dalon Westergreen
Signed-off-by: Siew Chin Lim
---
v4:
- Replace CONFIG_TARGET_SOCFPGA_STRATIX10/AGILEX with
CONFIG_TARGET_SOCFPGA_SOC64.
- Add this patch into 'VAB
for combined spl
and dtb
Siew Chin Lim (6):
arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)
arm: socfpga: cmd: Support 'vab' command
arm: socfpga: dts: soc64: Update filename in binman node of FIT image
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/Kconfig| 6 +++---
arch/arm/mach-socfpga/Kconfig | 5 +
arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +--
arch
FIT image of Vendor Authentication Coot (VAB) contains signed images.
Signed-off-by: Siew Chin Lim
---
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
b/arch/arm/dts
Support 'vab' command to perform vendor authentication.
Command format: vab addr len
Authorize 'len' bytes starting at 'addr' via vendor public key
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/vab.c| 34 +++
Secure Device Manager (SDM)
for authentication. U-Boot will validate the SHA384 of the image
against the SHA384 hash stored in the VAB certificate before
sending the image to SDM for authentication.
Signed-off-by: Siew Chin Lim
---
v5:
- In arch/arm/mach-socfpga/board.c
- Move '#if IS_EN
Booting Agilex with Vendor Authorized Boot.
Signed-off-by: Siew Chin Lim
---
.../{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}| 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
copy configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig}
(92%)
CONFIG_BOOTCOMMAND have been moved to Kconfig.boot. This patch
move the CONFIG_BOOTCOMMAND macro from socfpga_soc64_common.h to
*_defconfig file for both Stratix 10 and Agilex.
Signed-off-by: Siew Chin Lim
---
configs/socfpga_agilex_atf_defconfig| 2 ++
configs/socfpga_agilex_defconfig
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