Hi, Wadim,
Thanks for the review.
On 30/05/24 17:48, Wadim Egorov wrote:
Hi Santhosh,
thanks for this series!
Am 23.05.24 um 07:04 schrieb Santhosh Kumar K:
As there are few redundant functions in board/ti/*/evm.c files, pull
them to a common location of access to reuse and include the
ev (1):
ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming
Neha Malcom Francis (1):
drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC
Santhosh Kumar K (8):
ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve
'calculations restricted to 32 bits' issue
ed-off-by: Georgi Vlaev
Signed-off-by: Santhosh Kumar K
Reviewed-by: Neha Malcom Francis
---
drivers/ram/k3-ddrss/k3-ddrss.c | 122 +---
1 file changed, 114 insertions(+), 8 deletions(-)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss
d
size of RAM's banks from the device tree memory node, and store in a
64 bit device private data which can be used for ECC reserved memory
calculation, Setting ECC range and Fixing up bank size in device tree
when ECC is enabled.
Signed-off-by: Santhosh Kumar K
Reviewed-by: Neha Malcom Franc
Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts
by setting the respective bits in the DDRSS_V2A_INT_SET_REG register.
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-ddrss/k3-ddrss.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/ram/k3-ddrss/k3
Setup the ECC region's start and range using the device private data,
ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and
range of ECC regions from 32 bits to 64 bits to accommodate for
DDR greater than or equal to 4GB.
Signed-off-by: Santhosh Kumar K
Reviewed-by:
From: Neha Malcom Francis
Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL
only when the config has been enabled.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/Kconfig | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/ram/Kconfig b/drivers/
As there are few redundant functions in board/ti/*/evm.c files, pull
them to a common location of access to reuse.
Signed-off-by: Santhosh Kumar K
---
board/ti/common/k3-ddr-init.c | 75 +++
board/ti/common/k3-ddr-init.h | 15 +++
2 files changed, 90
Remove the redundant DDR functions and include the common file to
access the functions.
Signed-off-by: Santhosh Kumar K
---
board/ti/am64x/evm.c | 71
1 file changed, 5 insertions(+), 66 deletions(-)
diff --git a/board/ti/am64x/evm.c b/board/ti
Remove the redundant DDR functions and include the common file to
access the functions.
Signed-off-by: Santhosh Kumar K
---
board/ti/am62x/evm.c | 61 +---
1 file changed, 6 insertions(+), 55 deletions(-)
diff --git a/board/ti/am62x/evm.c b/board/ti
Call k3-ddrss driver through fixup_ddr_driver_for_ecc() to fixup the
device tree and resize the available amount of DDR, if ECC is enabled.
Otherwise, fixup the device tree using the regular
fdt_fixup_memory_banks().
Signed-off-by: Santhosh Kumar K
---
board/ti/am62ax/evm.c | 16
Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.
Signed-off-by: Santhosh Kumar K
---
arch/arm/dts/k3-am62a-ddr.dtsi | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/k3-am62a-ddr.dtsi b/arch/arm/dts/k3-am62a
s: j7*_evm_r5_defconfig: Set NR_DRAM_BANKS to 2
Santhosh Kumar K (5):
ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve
'calculations restricted to 32 bits' issue
ram: k3-ddrss: Setup ECC region start and range
ram: k3-ddrss: Enable ECC interrupts
board: ti: Pul
tible with devices with both 16-bit LPDDR4 and
32-bit LPDDR4 interfaces (e.g J721E).
[1] AM62x: https://www.ti.com/lit/pdf/spruiv7
[2] DRA829/TDA4VM: https://www.ti.com/lit/zip/spruil1
Signed-off-by: Georgi Vlaev
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-ddrss/k3-ddrss.c | 122 +
d
size of RAM's banks from the device tree memory node, and store in a
64 bit device private data which can be used for ECC reserved memory
calculation, Setting ECC range and Fixing up bank size in device tree
when ECC is enabled.
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-d
Setup the ECC region's start and range using the device private data,
ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and
range of ECC regions from 32 bits to 64 bits to accommodate for
DDR greater than or equal to 4GB.
Signed-off-by: Santhosh Kumar K
---
drivers/r
Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts
by setting the respective bits in the DDRSS_V2A_INT_SET_REG register.
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-ddrss/k3-ddrss.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/ram/k3-ddrss/k3
From: Neha Malcom Francis
Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL
only when the config has been enabled.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/Kconfig | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/ram/Kconfig b/drivers/
From: Neha Malcom Francis
Set CONFIG_NR_DRAM_BANKS to 2 as we have two banks described in the
memory/ node for lower and higher addressible DDR regions.
This allows use of FDT functions from fdt_support.c to set up and fixup
the memory/ node correctly.
Signed-off-by: Neha Malcom Francis
---
c
ers present.
Signed-off-by: Santhosh Kumar K
Signed-off-by: Neha Malcom Francis
---
board/ti/am62ax/evm.c | 17 ---
board/ti/am62px/evm.c | 18 ---
board/ti/am62x/evm.c | 63 -
board/ti/am64x/evm.c |
Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.
Signed-off-by: Santhosh Kumar K
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-am62a-ddr.dtsi | 7 ---
arch/arm/dts/k3-j721s2-ddr.dtsi | 12
arch/arm/dts/k3-j784s4
BIST engine for ECC priming
Neha Malcom Francis (2):
drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC
configs: j7*_evm_r5_defconfig: Set NR_DRAM_BANKS to 2
Santhosh Kumar K (5):
ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve
'calculations restricted to 32 bits&#x
tible with devices with both 16-bit LPDDR4 and
32-bit LPDDR4 interfaces (e.g J721E).
[1] AM62x: https://www.ti.com/lit/pdf/spruiv7
[2] DRA829/TDA4VM: https://www.ti.com/lit/zip/spruil1
Signed-off-by: Georgi Vlaev
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-ddrss/k3-ddrss.c | 122 +
d
size of RAM's banks from the device tree memory node, and store in a
64 bit device private data which can be used for ECC reserved memory
calculation, Setting ECC range and Fixing up bank size in device tree
when ECC is enabled.
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-d
Setup the ECC region's start and range using the device private data,
ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and
range of ECC regions from 32 bits to 64 bits to accommodate for
DDR greater than or equal to 4GB.
Signed-off-by: Santhosh Kumar K
---
drivers/r
Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts
by setting the respective bits in the DDRSS_V2A_INT_SET_REG register.
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-ddrss/k3-ddrss.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/ram/k3-ddrss/k3
From: Neha Malcom Francis
Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL
only when the config has been enabled.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/Kconfig | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/ram/Kconfig b/drivers/r
From: Neha Malcom Francis
Set CONFIG_NR_DRAM_BANKS to 2 as we have two banks described in the
memory/ node for lower and higher addressible DDR regions.
This allows use of FDT functions from fdt_support.c to set up and fixup
the memory/ node correctly.
Signed-off-by: Neha Malcom Francis
---
c
ers present.
Signed-off-by: Santhosh Kumar K
Signed-off-by: Neha Malcom Francis
---
board/ti/am62ax/evm.c | 17 ---
board/ti/am62px/evm.c | 18 ---
board/ti/am62x/evm.c | 63 -
board/ti/am64x/evm.c |
Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.
Signed-off-by: Santhosh Kumar K
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-am62a-ddr.dtsi | 7 ---
arch/arm/dts/k3-j721s2-ddr.dtsi | 12
arch/arm/dts/k3-j784s4
On 31/01/24 11:32, Santhosh Kumar K wrote:
This series is to:
1. Enable ECC priming with BIST engine (Patch 1)
2. Add a function to store base address and size of RAM's banks
in a 64 bit device private data (Patch 2)
3. Setup the ECC region start and range (Patch 3)
4. Enable ECC
tible with devices with both 16-bit LPDDR4 and
32-bit LPDDR4 interfaces (e.g J721E).
[1] AM62x: https://www.ti.com/lit/pdf/spruiv7
[2] DRA829/TDA4VM: https://www.ti.com/lit/zip/spruil1
Signed-off-by: Georgi Vlaev
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-ddrss/k3-ddrss.c | 122 +
for ECC priming
Neha Malcom Francis (2):
drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC
configs: j7*_evm_r5_defconfig: Set NR_DRAM_BANKS to 2
Santhosh Kumar K (5):
ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve
'calculations restricted to 32 bits' issue
ers present.
Signed-off-by: Santhosh Kumar K
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/Makefile | 2 +-
arch/arm/mach-k3/include/mach/k3-ddr.h | 15 +
arch/arm/mach-k3/k3-ddr.c | 88 ++
board/ti/am62ax/evm.c |
Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.
Signed-off-by: Santhosh Kumar K
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-am62a-ddr.dtsi | 7 ---
arch/arm/dts/k3-j721s2-ddr.dtsi | 12
arch/arm/dts/k3-j784s4
Setup the ECC region's start and range using the device private data,
ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and
range of ECC regions from 32 bits to 64 bits to accommodate for
DDR greater than or equal to 4GB.
Signed-off-by: Santhosh Kumar K
---
drivers/r
From: Neha Malcom Francis
Set CONFIG_NR_DRAM_BANKS to 2 as we have two banks described in the
memory/ node for lower and higher addressible DDR regions.
This allows use of FDT functions from fdt_support.c to set up and fixup
the memory/ node correctly.
Signed-off-by: Neha Malcom Francis
---
c
Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts
by setting the respective bits in the DDRSS_V2A_INT_SET_REG register.
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-ddrss/k3-ddrss.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/ram/k3-ddrss/k3
From: Neha Malcom Francis
Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL
only when the config has been enabled.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/Kconfig | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/ram/Kconfig b/drivers/r
d
size of RAM's banks from the device tree memory node, and store in a
64 bit device private data which can be used for ECC reserved memory
calculation, Setting ECC range and Fixing up bank size in device tree
when ECC is enabled.
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-d
Hi, Tom,
On 30/12/24 23:12, Tom Rini wrote:
Hey all,
As part of testing the SPI fixes, I tracked down a problem on my AM64X
SR1.0 GP to the above series. With the series applied, I get:
=> sf probe
jedec_spi_nor flash@0: non-uniform erase sector maps are not supported yet.
SF: Detected s28hs512
Hi, Tom,
On 01/01/25 04:21, Tom Rini wrote:
On Fri, Dec 13, 2024 at 04:01:29PM +0530, Santhosh Kumar K wrote:
As there are few redundant functions in board/ti/*/evm.c files, pull
them to a common location of access to reuse and include the common file
to access the functions.
Call k3-ddrss
tible with devices with both 16-bit LPDDR4 and
32-bit LPDDR4 interfaces (e.g J721E).
[1] AM62x: https://www.ti.com/lit/pdf/spruiv7
[2] DRA829/TDA4VM: https://www.ti.com/lit/zip/spruil1
Signed-off-by: Georgi Vlaev
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-ddrss/k3-ddrss.c | 122 +
devices.
v1: https://lore.kernel.org/u-boot/20240131060213.1128024-1-s...@ti.com/
Signed-off-by: Santhosh Kumar K
Tested-by: Wadim Egorov
Georgi Vlaev (1):
ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming
Neha Malcom Francis (2):
drivers: ram: Kconfig: Add CONFIG_K3_INLI
Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.
Signed-off-by: Santhosh Kumar K
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-am62a-ddr.dtsi | 7 ---
arch/arm/dts/k3-j721s2-ddr.dtsi | 12
arch/arm/dts/k3-j784s4
d
size of RAM's banks from the device tree memory node, and store in a
64 bit device private data which can be used for ECC reserved memory
calculation, Setting ECC range and Fixing up bank size in device tree
when ECC is enabled.
Signed-off-by: Santhosh Kumar K
Reviewed-by: Wadim Egorov
Setup the ECC region's start and range using the device private data,
ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and
range of ECC regions from 32 bits to 64 bits to accommodate for
DDR greater than or equal to 4GB.
Signed-off-by: Santhosh Kumar K
---
drivers/r
The functionality of enabling Inline ECC is now controlled by
CONFIG_K3_INLINE_ECC. So, remove the support for 'ti,ecc-enable'
property to avoid redundancy and to ensure the Inline ECC feature is
mananged through build-time config.
Signed-off-by: Santhosh Kumar K
Reviewed-by: Wa
Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts
by setting the respective bits in the DDRSS_V2A_INT_SET_REG register.
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-ddrss/k3-ddrss.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/ram/k3-ddrss/k3
From: Neha Malcom Francis
Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL
only when the config has been enabled.
Signed-off-by: Neha Malcom Francis
Signed-off-by: Santhosh Kumar K
Reviewed-by: Wadim Egorov
---
drivers/ram/Kconfig | 10 ++
1 file changed
ers present.
Signed-off-by: Santhosh Kumar K
Signed-off-by: Neha Malcom Francis
Reviewed-by: Wadim Egorov
---
arch/arm/mach-k3/Makefile | 2 +-
arch/arm/mach-k3/include/mach/k3-ddr.h | 15 ++
arch/arm/mach-k3/k3-ddr.c | 72 +
board/ti/am6
Signed-off-by: Santhosh Kumar K
---
arch/arm/mach-k3/Kconfig | 3 +++
configs/am62ax_evm_a53_defconfig | 1 -
configs/am62px_evm_a53_defconfig | 1 -
configs/am62x_evm_a53_defconfig | 1 -
configs/am62x_evm_r5_defconfig| 1 -
configs/am64x_evm_a53_defconfig
Hi, Manorit,
On 23/10/24 10:14, Manorit Chawdhry wrote:
Hi Santhosh,
On 10:10-20241021, Santhosh Kumar K wrote:
As R5 is a 32 bit processor, the RAM banks' base and size calculation
is restricted to 32 bits, which results in wrong values if bank's base
is greater than 32 bits or b
Hi, Bryan,
On 23/10/24 20:09, Bryan Brattlof wrote:
On October 21, 2024 thus sayeth Santhosh Kumar K:
As R5 is a 32 bit processor, the RAM banks' base and size calculation
is restricted to 32 bits, which results in wrong values if bank's base
is greater than 32 bits or bank's
Hi, everyone,
On 21/10/24 10:10, Santhosh Kumar K wrote:
Hello,
This series is to:
Add support for Inline ECC in DDR for AM64X, AM62X, AM62AX, AM62PX,
J721S2 and J784S4 devices.
(1/8) Enable ECC priming with BIST engine
(2/8) Add a function to store base address and size of RAM's
Hi, Bryan,
On 23/10/24 20:18, Bryan Brattlof wrote:
On October 21, 2024 thus sayeth Santhosh Kumar K:
From: Neha Malcom Francis
Set CONFIG_NR_DRAM_BANKS to 2 as we have two banks described in the
memory/ node for lower and higher addressible DDR regions.
This allows use of FDT functions
Hi, Bryan and Neha,
On 24/10/24 09:33, Neha Malcom Francis wrote:
Hi Bryan
On 23/10/24 20:15, Bryan Brattlof wrote:
On October 21, 2024 thus sayeth Santhosh Kumar K:
From: Neha Malcom Francis
Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into
R5 SPL
only when the config
Hi, Neha,
On 22/10/24 14:52, Neha Malcom Francis wrote:
Hi Santhosh
On 21/10/24 10:10, Santhosh Kumar K wrote:
Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.
Signed-off-by: Santhosh Kumar K
Signed-off-by: Neha Malcom Francis
---
arch
Hi, Wadim,
On 22/10/24 15:34, Wadim Egorov wrote:
Hi Santhosh,
Am 21.10.24 um 06:40 schrieb Santhosh Kumar K:
As there are few redundant functions in board/ti/*/evm.c files, pull
them to a common location of access to reuse and include the common file
to access the functions.
Call k3-ddrss
eorgi Vlaev (1):
ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming
Neha Malcom Francis (2):
drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC
arm: mach-k3: Set NR_DRAM_BANKS to 2
Santhosh Kumar K (6):
arm: dts: k3-*-ddr: Add ss_cfg reg entry
ram: k3-ddrss: Add k3_ddrss_ddr_ban
tible with devices with both 16-bit LPDDR4 and
32-bit LPDDR4 interfaces (e.g J721E).
[1] AM62x: https://www.ti.com/lit/pdf/spruiv7
[2] DRA829/TDA4VM: https://www.ti.com/lit/zip/spruil1
Signed-off-by: Georgi Vlaev
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-ddrss/k3-ddrss.c | 122 +
d
size of RAM's banks from the device tree memory node, and store in a
64 bit device private data which can be used for ECC reserved memory
calculation, Setting ECC range and Fixing up bank size in device tree
when ECC is enabled.
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-d
Add ss_cfg memory region which maps the DDRSS configuration region
for the memory controller node.
Signed-off-by: Santhosh Kumar K
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-am62a-ddr.dtsi | 7 ---
arch/arm/dts/k3-j721s2-ddr.dtsi | 12
arch/arm/dts/k3-j784s4
Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts
by setting the respective bits in the DDRSS_V2A_INT_SET_REG register.
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k3-ddrss/k3-ddrss.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/ram/k3-ddrss/k3
Setup the ECC region's start and range using the device private data,
ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and
range of ECC regions from 32 bits to 64 bits to accommodate for
DDR greater than or equal to 4GB.
Signed-off-by: Santhosh Kumar K
---
drivers/r
ers present.
Signed-off-by: Santhosh Kumar K
Signed-off-by: Neha Malcom Francis
---
arch/arm/mach-k3/Makefile | 2 +-
arch/arm/mach-k3/include/mach/k3-ddr.h | 15 ++
arch/arm/mach-k3/k3-ddr.c | 72 +
board/ti/am62ax/evm.c |
From: Neha Malcom Francis
Set CONFIG_NR_DRAM_BANKS to 2 as we have two banks described in the
memory/ node for lower and higher addressible DDR regions.
This allows use of FDT functions from fdt_support.c to set up and fix up
the memory/ node correctly.
Signed-off-by: Neha Malcom Francis
---
The functionality of enabling Inline ECC is now controlled by
CONFIG_K3_INLINE_ECC. So, remove the support for 'ti,ecc-enable'
property to avoid redundancy and to ensure the Inline ECC feature is
mananged through build-time config.
Signed-off-by: Santhosh Kumar K
---
drivers/ram/k
From: Neha Malcom Francis
Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL
only when the config has been enabled.
Signed-off-by: Neha Malcom Francis
---
drivers/ram/Kconfig | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/ram/Kconfig b/drivers/r
: Santhosh Kumar K
---
Tested on AM64x, AM62Ax, AM62Px.
Logs: https://gist.github.com/santhosh21/6dcdeb9a118c13732f858a1baca7dc4c
---
drivers/ram/k3-ddrss/k3-ddrss.c | 32 +---
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b
Add UBIFS support on top of MTD devices by enabling the required
configs.
Signed-off-by: Santhosh Kumar K
---
configs/am62px_evm_a53_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig
index 4b5d1ec1613c
Add UBIFS support on top of MTD devices by enabling the required
configs.
Signed-off-by: Santhosh Kumar K
---
configs/am64x_evm_a53_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index 3f002aecfa7e
Add UBIFS support on top of MTD devices by enabling the required
configs.
Signed-off-by: Santhosh Kumar K
---
configs/am62x_evm_a53_defconfig | 7 +++
1 file changed, 7 insertions(+)
diff --git a/configs/am62x_evm_a53_defconfig b/configs/am62x_evm_a53_defconfig
index d9596cb72242
This series adds support for UBIFS in AM64x, AM62x, AM62Px.
Test logs: https://gist.github.com/santhosh21/be687f10086fe3b02d76cf5126a99861
Signed-off-by: Santhosh Kumar K
Santhosh Kumar K (3):
configs: am64x: Add UBIFS support
configs: am62x: Add UBIFS support
configs: am62px: Add UBIFS
Update the DDR Configurations for AM62Ax SK according to the SysConfig
DDR Configuration tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02.
Signed-off-by: Santhosh Kumar K
---
arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi | 50 ++--
1 file changed, 26 insertions(+), 24
Update the DDR Configurations for AM62x SK according to the SysConfig
DDR Configuration tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02.
Signed-off-by: Santhosh Kumar K
---
arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi | 14 --
1 file changed, 8 insertions(+), 6 deletions
Update the DDR Configurations for AM62x LP SK according to the SysConfig
DDR Configuration tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02.
Signed-off-by: Santhosh Kumar K
---
arch/arm/dts/k3-am62-lp4-50-800-800.dtsi | 16 +---
1 file changed, 9 insertions(+), 7 deletions
Update the DDR Configurations for AM64x EVM according to the SysConfig
DDR Configuration tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02.
Signed-off-by: Santhosh Kumar K
---
arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi | 16 +---
1 file changed, 9 insertions(+), 7 deletions
Update the DDR Configurations for AM62Px SK according to the SysConfig
DDR Configuration tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02.
Signed-off-by: Santhosh Kumar K
---
arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff
Signed-off-by: Santhosh Kumar K
Santhosh Kumar K (5):
arm: dts: k3-am64: Update DDR Configurations
arm: dts: k3-am62x: Update DDR Configurations
arm: dts: k3-am62-lp: Update DDR Configurations
arm: dts: k3-am62a: Update DDR Configurations
arm: dts: k3-am62p: Update DDR Configurations
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