: Philip Oberfichtner
Reviewed-by: Marek Vasut
---
Changes in v3:
- Reviewed by Marek
Changes in v2:
- convert to livetree (rebase on commit 5a605b7c86152)
board/dhelectronics/common/Makefile| 10
board/dhelectronics/common/dh_common.c | 65
To reduce code duplication, let the stm32 based DH boards use the common
code for setting up their MAC addresses.
Signed-off-by: Philip Oberfichtner
Tested-by: Marek Vasut
Reviewed-by: Marek Vasut
---
Changes in v3:
- Reviewed by Marek
Changes in v2:
- convert to livetree
: Philip Oberfichtner
Reviewed-by: Marek Vasut
---
(no changes since v3)
Changes in v3:
- Reviewed by Marek
Changes in v2:
- convert to livetree (rebase on commit 5a605b7c86152)
board/dhelectronics/common/Makefile| 10
board/dhelectronics/common/dh_common.c | 65
To reduce code duplication, let the imx6 based DH boards use the common
code for setting up their MAC addresses.
Signed-off-by: Philip Oberfichtner
Tested-by: Marek Vasut
Reviewed-by: Marek Vasut
---
(no changes since v3)
Changes in v3:
- Reviewed by Marek
Changes in v2
v3:
- Entire series reviewed by Marek
Changes in v2:
- Tested-by Marek
- convert to livetree (rebase on commit 5a605b7c86152)
- Fix spelling
Philip Oberfichtner (4):
board: dhelectronics: Implement common MAC address functions
ARM: imx6: DH: Use common MAC
To reduce code duplication, let the imx8 based DH boards use the common
code for setting up their MAC addresses.
Signed-off-by: Philip Oberfichtner
Tested-by: Marek Vasut
Reviewed-by: Marek Vasut
---
(no changes since v3)
Changes in v3:
- Reviewed by Marek
Changes in v2
To reduce code duplication, let the stm32 based DH boards use the common
code for setting up their MAC addresses.
Signed-off-by: Philip Oberfichtner
Tested-by: Marek Vasut
Reviewed-by: Marek Vasut
Reviewed-by: Patrick Delaunay
---
Changes in v4:
- Replace printf() by log_err
for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable()
Signed-off-by: Philip Oberfichtner
---
arch/arm/lib/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index c603fe61bc..ac1d4245bb 100644
--- a/arch/arm/lib
From: Marek Vasut
Enable d-cache early in SPL right after DRAM is started up.
This reduces U-Boot proper load time by 650ms when loaded
from SPI NOR.
Signed-off-by: Marek Vasut
Signed-off-by: Philip Oberfichtner
---
board/dhelectronics/dh_imx6/dh_imx6_spl.c | 27 +++
1
On Thu, 2022-08-04 at 11:02 +0200, Marek Vasut wrote:
> On 8/4/22 10:15, Philip Oberfichtner wrote:
> > Before this commit, the SPL could enable the PL310 L2 cache [1],
> > but the
> > cache maintenance functions from cache-pl310.c were only useable
> > for
> &g
for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable()
Signed-off-by: Philip Oberfichtner
---
(no changes since v1)
arch/arm/lib/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index c603fe61bc..ac1d4245bb
From: Marek Vasut
Enable d-cache early in SPL right after DRAM is started up.
This reduces U-Boot proper load time by 650ms when loaded
from SPI NOR.
Signed-off-by: Marek Vasut
Signed-off-by: Philip Oberfichtner
---
Changes in v2:
- Add comment to explain the relevance of
On Thu, 2022-08-04 at 07:05 -0400, Tom Rini wrote:
> On Thu, Aug 04, 2022 at 12:56:45PM +0200, Philip Oberfichtner wrote:
>
> > Before this commit, the SPL could enable the PL310 L2 cache [1],
> > but the
> > cache maintenance functions from cache-pl310.c were only use
; > + sha256_csum_wd(pbuf, buf_len, pout,
> > CHUNKSZ_SHA256);
> > + return 0;
>
> How about adding “#ifdef CONFIG_SHA1” and “#ifdef CONFIG_SHA256” here
> ? Then it can depend on users’ selection to determine the fallback
>
> Best regards,
> Ye Li
>
> > }
> >
> > size = ALIGN(buf_len, ARCH_DMA_MINALIGN);
> > --
> > 2.25.1
Is this patch still active? The change request is already two months
old. If the original patch request is abandoned, should I contribute a
[PATCH v2]?
Best Regards,
Philip Oberfichtner
This series adds a new bootcount driver. The required register definitions
and the actual driver are separated in two patches.
Philip Oberfichtner (2):
power: pfuze100: Add MEMx register definitions
bootcount: Add pmic pfuze100 bootcount driver
drivers/bootcount/Kconfig
Add missing MEMA - MEMD register definitions for PFUZE100.
Based on work from Heiko Schocher .
Signed-off-by: Philip Oberfichtner
---
include/power/pfuze100_pmic.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
index
Use the MEMA - MEMD registers on the PFUZE100 as bootcount
registers.
Based on work from Heiko Schocher .
Signed-off-by: Philip Oberfichtner
---
drivers/bootcount/Kconfig | 7 ++
drivers/bootcount/Makefile | 1 +
drivers/bootcount/bootcount_pmic_pfuze100.c
The Bosch ACC (Air Center Control) Board is based on the i.MX6D.
Signed-off-by: Philip Oberfichtner
---
This board supports depends on:
- "Add pmic bootcount driver", patchwork id 287976
- "crypto/fsl: Fallback to SW sha1/256 is misaligned buffers",
patchwork id 27052
This series adds a new bootcount driver. The required register definitions
and the actual driver are separated in two patches.
Changes in v2:
- Migrated bootcount driver to driver model
- Introduced error handling. Previously errors were ignored.
Philip Oberfichtner (2):
power: pfuze100: Add
Add missing MEMA - MEMD register definitions for PFUZE100.
Based on work from Heiko Schocher .
Signed-off-by: Philip Oberfichtner
---
(no changes since v1)
include/power/pfuze100_pmic.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/power/pfuze100_pmic.h b/include/power
Use the MEMA - MEMD registers on the PFUZE100 as bootcount
registers.
Based on work from Heiko Schocher .
Signed-off-by: Philip Oberfichtner
---
Changes in v2:
- Migrated bootcount driver to driver model
- Introduced error handling. Previously errors were ignored.
drivers/bootcount/Kconfig
On Fri, 2022-03-11 at 19:25 -0700, Simon Glass wrote:
> Hi Philip,
>
> On Fri, 25 Feb 2022 at 06:56, Philip Oberfichtner
> wrote:
> > Use the MEMA - MEMD registers on the PFUZE100 as bootcount
> > registers.
> >
> > Based on work from Heiko Schocher .
&g
On Thu, Aug 01, 2024 at 08:20:17AM -0600, Tom Rini wrote:
> On Wed, Jul 17, 2024 at 02:29:01PM +0200, Philip Oberfichtner wrote:
>
> > This patch series implements the dwc_eth_qos glue driver for Intel SOCs.
> > Before doing that, a few general adaptions to the dwc_eth_qos.c m
printf format string
Changes in V3:
- Replace mfence() with mb()
- Clean-up eqos_get_base_addr()
- Several style fixes for dwc_eth_qos_intel
Philip Oberfichtner (5):
x86: provide mb() macro
net: dwc_eth_qos: Fix header to be self-contained
net: dwc_eth_qos: Adapt
Implement a x86 memory barrier mb(). Furthermore, remove the previously
used mfence() function, which does the same thing.
The mb() macro is now equivalent to Linux (v6.9):
linux/arch/x86/include/asm/barrier.h
Signed-off-by: Philip Oberfichtner
---
Notes:
Changes in V4: None
Before this commit, usage of this header relied on a specific include
order. Fix it by including all dependencies.
Signed-off-by: Philip Oberfichtner
Reviewed-by: Marek Vasut
---
Notes:
Changes in V4: None
Changes in V3: None
drivers/net/dwc_eth_qos.h | 5 -
1 file changed, 4
off-by: Philip Oberfichtner
---
Notes:
Changes in V4:
- Fix printf format string to account for 32-bit fdt_addr_t
Changes in V3:
Factor out eqos_get_base_addr_common() in order to avoid introducing a new
callback function.
drivers/net/dwc_eth_qos.c
PCI devices do not necessarily use a device tree. Implement a bind()
function to assign unique device names in that case.
Signed-off-by: Philip Oberfichtner
---
Notes:
Changes in V4: None
Changes in V3: None
drivers/net/dwc_eth_qos.c | 16
1 file changed, 16
Add dwc_eth_qos glue driver for the Intel Elkhart-Lake SOC.
Signed-off-by: Philip Oberfichtner
---
Notes:
Changes in V4: None
Changes in V3:
- update linux reference to current stable
- replace pr_err by dev_err
- drop __prefix from local function names
- use
Hi all,
Seems there is no more comments to the series. Can we get it merged
then?
Best regards,
Philip
On Fri, Aug 02, 2024 at 11:25:34AM +0200, Philip Oberfichtner wrote:
> This patch series implements the dwc_eth_qos glue driver for Intel SOCs.
> Before doing that, a few general adapti
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