[U-Boot] ubi part failing on NAND

om main input shell. My last sync with the denx git was when 2.6.31 was released. Here is my version: => ver U-Boot 2009.08-00213-gfdf80f7 (Dec 17 2009 - 12:57:07) Jeff Angielski The PTR Group www.theptrgroup.com ___ U-Boot mailing list U-Boot@l

Re: [U-Boot] ubi part failing on NAND

>> Jeff, >> >> On Thursday 17 December 2009 22:09:03 Jeff Angielski wrote: >>> The "ubi part" command is failing for me on my PowerPC 85xx board. I am >>> not trying to do anything special, just create the partitions and >>> volumes so that I can tr

Re: [U-Boot] ubi part failing on NAND

es: 128 UBI: wear-leveling threshold:4096 UBI: number of internal volumes: 1 UBI: number of user volumes: 0 UBI: available PEBs: 2021 UBI: total number of reserved PEBs: 24 UBI: number of PEBs reserved for bad PEB handling: 20 UBI: max/mean erase counter: 0/0 => -- Je

[U-Boot] cross compiling fw_printenv on big endian

than resort of hacking the crc32.c file. -- Jeff Angielski The PTR Group www.theptrgroup.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] cross compiling fw_printenv on big endian

tools. diff --git a/lib_generic/crc32.c b/lib_generic/crc32.c index 468b397..27335a3 100644 --- a/lib_generic/crc32.c +++ b/lib_generic/crc32.c @@ -163,7 +163,7 @@ const uint32_t * ZEXPORT get_crc_table() #endif /* = */ -# ifdef __LITT

Re: [U-Boot] cross compiling fw_printenv on big endian

Joakim Tjernlund wrote: Jeff Angielski wrote on 2010/03/17 16:10:50: Joakim Tjernlund wrote: Wolfgang Denk wrote on 2010/03/17 12:57:31: Dear Joakim Tjernlund, In message you wrote: hmm, I recently discovered that normal user space headers always define both __LITTLE_ENDIAN and

[U-Boot] [PATCH] env: fix endian ordering in crc table

The crc table was being built as little endian for big endian targets. This would cause fw_printenv to always fail with "Warning: Bad CRC, using default environment" messages. Signed-off-by: Jeff Angielski --- lib_generic/crc32.c |2 +- 1 files changed, 1 insertions(+), 1

[U-Boot] Bad CPU identification on MPC8544DS

MHz, DDR:200 MHz (400 MT/s data rate), LBC:25 MHz L1:D-cache 32 kB enabled I-cache 32 kB enabled Board: MPC8544DS, System ID: 0x12, System Version: 0x20, FPGA Version: 0x31 -- Jeff Angielski The PTR

Re: [U-Boot] Bad CPU identification on MPC8544DS

On Tue, 2009-03-03 at 14:04 -0500, jeff angielski wrote: > Despite the SVR being the same (0x803c0011), the latest u-boot is > misidentifying the CPU when compared against the original 1.3.0 u-boot. > The CPU is a 8544E but u-boot is reporting 8533E. > > The wierd part of this is