Hi,
I need an info, what are the changes that can be added to plain u-boot that
supports a particular board.
Please point-out any specific doc or links.
Thanks for your time.
Regards,
Jagan.
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t code.
I found some hack for this, but does it a valid issue or did I make any
mistake.
Request for your help.
Regards,
Jagan.
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.
The reason I am writing different driver for numonyx because it will be a
bit messy If we keep
on adding extra things(specific to numonyx) to stmicro.c
Please let me know your views, if my suggestion is good I will send the
patch.
If am wrong with my understanding, please send an optimized su
sk subimage load address!
Ramdisk image is corrupt or invalid
So, I was added Load, Entry address and also OS tag on image.c.
Now mkimage is able to include these details and it's works fine.
Regards,
Jagan.
Jagannadha Sutradharudu Teki (1):
image/FIT: Add ramdisk load, entry address and OS t
From: Jagannadha Sutradharudu Teki <402ja...@gmail.com>
This patch adds support to include Load, Entry address and OS tag
of ramdisk on to FIT image through mkimage tool.
Signed-off-by: Jagannadha Sutradharudu Teki <402ja...@gmail.com>
---
common/image.c |7 ---
1 files changed, 4 insert
Any point to consider this..or we have any solution that may not require
this change?
Regards,
Jagan.
On Sat, Jul 28, 2012 at 1:32 PM, Jagan <402ja...@gmail.com> wrote:
> From: Jagannadha Sutradharudu Teki <402ja...@gmail.com>
>
> This patch adds support to include Load,
lease send any suggestion or pointers. is that still need a few
more patches.
Regards,
Jagan.
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Hi,
I am getting compilation issues on v11.12 with CONFIG_SYS_INIT_SP_ADDR.
Actually my SD RAM size was 256MB.
Can any one tell me how can I configure this macro?...
I have seen a procedure to do while defining this macros on some boards on
denx tree
Regards,
Jagan
first defined
here
Regards,
Jagan.
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Hi Kever,
On Tue, 21 Feb 2023 at 15:08, Kever Yang wrote:
>
> Hi Jagan,
>
> On 2023/2/17 05:44, Jonas Karlman wrote:
>
> + prate = priv->cpll_hz;
>
> Should be gpll_hz instead of cpll_hz.
>
> Do you have new patchset for this series, I will fix this if the
@ CONFIG_NET_RANDOM_ETHADDR=y
> CONFIG_SPL_REGMAP=y
> CONFIG_SPL_SYSCON=y
> CONFIG_SPL_CLK=y
> +CONFIG_FASTBOOT_BUF_ADDR=0xc00800
was this address used in bsp or used load addr? add it in
drivers/fastboot/Kconfig
Jagan.
On Thu, Feb 23, 2023 at 10:06 PM Manoj Sai
wrote:
>
> update the dwc3_device register offset in board_usb_init()
> for rk3568 platforms.
>
> Signed-off-by: Manoj Sai
> ---
Reviewed-by: Jagan Teki
nstead of moving this
redundant on each board file.
https://patchwork.ozlabs.org/project/uboot/patch/20230226132234.31949-2-abbaraju.manoj...@amarulasolutions.com/
So, please don't move.
Jagan.
Linux make maintenance easy and easy to fix.
If it is really needed then this change has to be in Linux.
Jagan.
to use latest vendor TPL on RK3328 without
> getting a size limit error running the mkimage command.
>
> Signed-off-by: Jonas Karlman
> Reviewed-by: Kever Yang
> ---
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki # roc-rk3328-cc
Reviewed-by: Simon Glass
> Reviewed-by: Kever Yang
> ---
Reviewed-by: Jagan Teki
Tested-by: Eugen Hristev
> ---
Reviewed-by: Jagan Teki
chip/Kconfig
> @@ -401,6 +401,14 @@ config TPL_ROCKCHIP_COMMON_BOARD
> common board is a basic TPL board init which can be shared for most
> of SoCs to avoid copy-paste for different SoCs.
>
> +config ROCKCHIP_EXTERNAL_TPL
> + bool "Use external TPL binary"
> + default y if ROCKCHIP_RK3568
Can you add RK3588 as well.
With that,
Reviewed-by: Jagan Teki
arlman
> Reviewed-by: Kever Yang
> ---
Reviewed-by: Jagan Teki
Hi Kever,
On Tue, 28 Feb 2023 at 15:30, Kever Yang wrote:
>
> Hi Jagan,
>
> On 2023/2/28 17:09, Jagan Teki wrote:
> > On Tue, 28 Feb 2023 at 14:34, Kever Yang wrote:
> >> rk3588 evb1 v10 is a evalution board from Rockchip, it is a dev board for
> >> rockchip
luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=4HDR%2BwouzdpqPFWPdvnZWRXSyjc94T%2F0pPHaXTYNrsM%3D&reserved=0
> >>
> >> Signed-off-by: Frieder Schrempf
> >> Cc: Jagan Teki
> >> Cc: Dario Binacchi
> >> Cc: Michael Nazzareno Trimarchi
>
bring more changes from Linux]
> Signed-off-by: Eugen Hristev
> ---
It would be good if it tested with any function, does it?
Jagan.
On Wed, 1 Mar 2023 at 14:54, Eugen Hristev wrote:
>
> On 3/1/23 10:53, Jagan Teki wrote:
> > On Wed, 1 Mar 2023 at 14:01, Eugen Hristev
> > wrote:
> >>
> >> From: Jianqun Xu
> >>
> >> Add support for Rockchip rk3588 variant of pinctrl.
On Wed, 1 Mar 2023 at 02:26, Jonas Karlman wrote:
>
> On 2023-02-28 10:19, Jagan Teki wrote:
> > On Sun, 26 Feb 2023 at 00:31, Jonas Karlman wrote:
> >>
> >> Rockchip SoCs typically use U-Boot TPL to initialize DRAM, then jumps
> >> back to BootRom to
bring more changes from Linux]
> Signed-off-by: Eugen Hristev
> ---
Reviewed-by: Jagan Teki
RK3588, add build steps for
> RK3588 to documentation and clean up CONFIG_BINMAN_FDT options.
>
> Signed-off-by: Jonas Karlman
> ---
Reviewed-by: Jagan Teki
*1
> SATA *2
> HDMI out *2
> HDMI IN *1
> USB2.0 Host *2
> USB3.0 Host *1
> Type C *1
> MIPI DSI panel
>
> dts Sync from Linux v6.2.
>
> Signed-off-by: Kever Yang
> ---
>
> Changes in v2:
> - Use the same dts name as kernel
Thanks.
Reviewed-by: Jagan Teki
6-orangepi-one-plus.dts
> @@ -37,7 +37,7 @@
>
> &mdio {
> ext_rgmii_phy: ethernet-phy@1 {
> - compatible = "ethernet-phy-ieee802.3-c22";
> + compatible = "ethernet-phy-id001c.c915",
> "ethernet-phy-ieee802.3-c22" ;
DT change has to be merged by the Linux tree first. Try to work on
that gets approved.
Thanks,
Jagan.
Hi Kever,
On Tue, Jun 6, 2023 at 10:39 PM Jagan Teki wrote:
>
> This series support fixes for RK3328 USB.
>
> Changes for v2:
> - collect Marek RB
> - update phy driver clockout_ctl for rk3328
> - retest on Xavier patches.
>
> Any inputs?
> Jagan.
>
> Jaga
Hi Kever,
On Sun, 11 Jun 2023 at 12:27, Jagan Teki wrote:
>
> Add missing suffix 'A' for Edgeble Neu6A SoM and IO boards.
>
> Fixes: <15b2d1fb727> ("board: rockchip: Add Edgeble Neural Compute
> Module 6")
> Signed-off-by: Jagan Teki
> ---
Please pick them up in MW.
Thanks,
Jagan.
Hi Tom,
Please pull this PR.
Summary:
- Add xtxtech spi-nor chip parts (Bruce Suen)
- Add bcm63xx-hsspi driver fixes (William Zhang)
CI:
https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/16886
thanks!
Jagan.
The following changes since commit
Sync the linux-next from below commit,
commit <1642bf66e270> ("arm64: dts: rockchip: add USB2 to
rk3588s-rock5a")
Also rops the duplicate usb nodes from rk3588s-u-boot.dtsi
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3588-edgeble-neu6a.dtsi | 1 -
arch/arm/dts/rk3588-edge
Now, edgeble-neu6 NCM IO boards support eMMC and SDMMC.
So, Update the spl-boot-order to include both.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi | 10 ++
arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi | 10 ++
2 files changed, 4 insertions
On Tue, 18 Jul 2023 at 02:36, Eugen Hristev wrote:
>
> On 7/17/23 18:42, Jagan Teki wrote:
> > Sync the linux-next from below commit,
> > commit <1642bf66e270> ("arm64: dts: rockchip: add USB2 to
> > rk3588s-rock5a")
> >
> > Also r
On Mon, 17 Jul 2023 at 22:12, Jonas Karlman wrote:
>
> Hi Jagan,
> On 2023-07-17 17:42, Jagan Teki wrote:
> > Sync the linux-next from below commit,
> > commit <1642bf66e270> ("arm64: dts: rockchip: add USB2 to
> > rk3588s-rock5a")
>
> Eugen sent
On Wed, Jul 19, 2023 at 1:30 PM Bruce Suen wrote:
>
>
> On 6/19/23 05:02, Jagan Teki wrote:
> > On Mon, Jun 19, 2023 at 1:51 PM Bruce Suen wrote:
> >>
> >> On 6/19/23 03:01, Jagan Teki wrote:
> >>> On Mon, Jun 19, 2023 at 12:25 PM Bruce Suen wrot
Now, edgeble-neu6 NCM IO boards support eMMC and SDMMC.
So, Update the spl-boot-order to include both.
Signed-off-by: Jagan Teki
---
Changes for v2:
- None
arch/arm/dts/rk3588-edgeble-neu6a-io-u-boot.dtsi | 10 ++
arch/arm/dts/rk3588-edgeble-neu6b-io-u-boot.dtsi | 10 ++
2
Sync the linux-next from below commit,
commit <1642bf66e270> ("arm64: dts: rockchip: add USB2 to
rk3588s-rock5a")
Also rops the duplicate usb nodes from rk3588s-u-boot.dtsi
Signed-off-by: Jagan Teki
---
Changes for v2:
- Keep sdhci modes for ROCK5B
arch/arm/dts/rk3588-ed
On Wed, Jul 19, 2023 at 2:46 PM Weijie Gao wrote:
>
> We don't really need to switch clk rate during operating SPIM controller.
> Get clk rate only once at driver probing.
>
> Signed-off-by: SkyLake.Huang
> Signed-off-by: Weijie Gao
> ---
Reviewed-by: Jagan Teki
IRQ and
> nothing will happen, the linux kernel may encounter panic during
> initializing the spim driver due to IRQ event happens before IRQ handler
> is properly setup.
>
> This patch clear IRQ bits to prevent this from happening.
>
> Signed-off-by: SkyLake.Huang
> Signed-off-by: Weijie Gao
> ---
Reviewed-by: Jagan Teki
er is busy.
>
> I notice that building this board does not produce a
> u-boot-rockchip.bin as I would expect.
Did you export ROCKCHIP_TPL, I can able to build neu6b-io.
Jagan.
Hi Simon,
On Wed, 26 Jul 2023 at 00:33, Simon Glass wrote:
>
> Hi Jagan,
>
> On Tue, 25 Jul 2023 at 12:56, Jagan Teki wrote:
> >
> > On Tue, 25 Jul 2023 at 23:33, Simon Glass wrote:
> > >
> > > Hi,
> > >
> > > What is the mainline sta
mmon spl_board_init")
> Cc: Quentin Schulz
> Signed-off-by: Quentin Schulz
> ---
Reviewed-by: Jagan Teki
no need to do this in the rk3399-specific code, so let's remove it.
>
> Cc: Quentin Schulz
> Tested-by: Xavier Drudis Ferran
> Signed-off-by: Quentin Schulz
> ---
Reviewed-by: Jagan Teki
/20220818124132.125304-1-ja...@edgeble.ai/
[3]
https://patchwork.ozlabs.org/project/uboot/cover/20220727174050.2214617-1-ja...@edgeble.ai/
Any inputs?
Jagan.
Jagan Teki (28):
ram: Mark ram-uclass depend on TPL_DM or SPL_DM
ram: rockchip: Add common ddr type configs
tools: rkcommon: Correct SPL size
ram-uclass is building irrespective of whether TPL_DM
or SPL_DM is enabled. So control the ram uclass build
based on TPL/SPL_DM.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/ram/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ram/Makefile b
We have common ddr types in rockchip or in general. So use
the common ddr type names instead of per Rockchip SoC to
avoid confusion.
The respective ddr type names will use on the associated
ddr SoC driver as these drivers are built per SoC at a time.
Signed-off-by: Jagan Teki
---
Changes for v2
Rockchip PX30 has 16KB sram, bootrom reserved 4KB as stack.
Correct it.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
tools/rkcommon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 0db45c2d41..1325aa83cb 100644
--- a/tools
DDR chip capacity is computed based on GRF split in some
Rockchip SoC's like PX30 and RV1126.
Add split argument in ddr print info so-that the respective
ddr driver will pass the grf split.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
arch/arm/includ
High row detection for non-8bit bw requires axi split.
So, update the existing high row detection code in order
to support full bw chips.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
.../include/asm/arch-rockchip/sdram_common.h | 2 +-
drivers/ram
Add full ddr pctl registers and bit masks for px30.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
.../asm/arch-rockchip/sdram_pctl_px30.h | 100 +-
drivers/ram/rockchip/sdram_pctl_px30.c| 6 +-
2 files changed, 101 insertions
Add DDR3 detection timings for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
.../sdram-rv1126-ddr3-detect-1056.inc | 72 +++
.../rockchip/sdram-rv1126-ddr3-detect-328.inc | 72 +++
.../rockchip
Add DDR loader parameters for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
.../rockchip/sdram-rv1126-loader_params.inc | 198 ++
1 file changed, 198 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram-rv1126
Control the ddr init print messages via RAM_ROCKCHIP_DEBUG
instead of printing by default.
This gives an option to configs to enable these prints or
not.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/ram/rockchip/sdram_rv1126.c | 38 +++--
1 file changed
Add LPDDR4 detection timings and support for RV1126.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
.../sdram-rv1126-lpddr4-detect-1056.inc | 78 +++
.../sdram-rv1126-lpddr4-detect-328.inc| 78 +++
.../sdram-rv1126-lpddr4-detect-396.inc
Some pins in rockchip are routed via Top GRF and PMU GRF
instead of direct regmap.
Add support to handle all these routing paths so that the
SoC pinctrl drivers will use them accordingly.
Signed-off-by: Jianqun Xu
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/pinctrl/rockchip
Add pinctrl driver for Rockchip RV1126.
Signed-off-by: Jianqun Xu
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rv1126.c | 416 ++
2 files changed, 417 insertions(+)
create mode
Add power-domain header for RV1126 SoC from description in TRM.
Signed-off-by: Elaine Zhang
Signed-off-by: Jagan Teki
---
Changes for v2:
- update filename
.../dt-bindings/power/rockchip,rv1126-power.h | 35 +++
1 file changed, 35 insertions(+)
create mode 100644 include/dt
Add the dt-bindings header for the Rockchip RV1126, that gets shared
between the clock controller and the clock references in the dts.
Signed-off-by: Finley Xiao
Signed-off-by: Jagan Teki
---
Changes for v2:
- update cru header
.../dt-bindings/clock/rockchip,rv1126-cru.h | 632
Add GRF header for Rockchip RV1126.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
.../include/asm/arch-rockchip/grf_rv1126.h| 251 ++
1 file changed, 251 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rv1126.h
diff --git a/arch/arm/include
Add clock driver support for Rockchip RV1126 SoC.
Signed-off-by: Joseph Chen
Signed-off-by: Jagan Teki
---
Changes for v2:
- update cru header
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk_rv1126.c | 1889 +
2 files changed, 1890 insertions
Add pinctrl definitions for Rockchip RV1126.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
arch/arm/dts/rv1126-pinctrl.dtsi | 302 +++
1 file changed, 302 insertions(+)
create mode 100644 arch/arm/dts/rv1126-pinctrl.dtsi
diff --git a/arch/arm/dts/rv1126
INT8/INT16
hybrid operation and computing power is up to 2.0TOPs.
This patch add basic core dtsi support.
Signed-off-by: Jon Lin
Signed-off-by: Sugar Zhang
Signed-off-by: Jagan Teki
---
Changes for v2:
- update header filename
arch/arm/dts/rv1126.dtsi | 500
Rockchip RV1126 is a high-performance vision processor SoC
for IPC/CVR, especially for AI related application.
Add arch core support for it.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
arch/arm/include/asm/arch-rv1126/boot0.h | 11
arch/arm/include/asm/arch-rv1126/gpio.h
Unsecure the dram area so that MMC, USB, and SFC controllers
can able to read data from dram.
Signed-off-by: Jason Zhu
Signed-off-by: Jagan Teki
---
Changes for v2:
- use IS_ENABLED
arch/arm/mach-rockchip/rv1126/rv1126.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch
Add common rv1126 include config.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
include/configs/rv1126_common.h | 42 +
1 file changed, 42 insertions(+)
create mode 100644 include/configs/rv1126_common.h
diff --git a/include/configs/rv1126_common.h b
Add support for rv1126 package header in mkimage tool.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 1325aa83cb..f18b6fad95 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
solutions.
Add support for it.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
.../rv1126-edgeble-edge-compute-module-0.dtsi | 329 ++
1 file changed, 329 insertions(+)
create mode 100644 arch/arm/dts/rv1126-edgeble-edge-compute-module-0.dtsi
diff --git a/arch/arm/dts
battery slot
- 40-pin expansion
Edge Compute Module 0 needs to mount on top of this Carrier board for
creating Edge Compute Module 0 Carrier platform.
Add support for it.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
arch/arm/dts/Makefile| 3 ++
arch/arm/dts/rv1126
Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
for Rockchip RV1126 SoC.
Both eMMC and SD boot are tested in Edge Compute Module 0.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
arch/arm/dts/rv1126-u-boot.dtsi | 62 +
1 file changed, 62
battery slot
- 40-pin expansion
Edge Compute Module 0 needs to mount on top of this Carrier board for
creating Edge Compute Module 0 Carrier platform.
Add support for it.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
.../rv1126-edgeble-ecm0-carrier-u-boot.dtsi | 10
arch/arm/mach
Add clock and reset unit header include for rv1126.
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
.../include/asm/arch-rockchip/cru_rv1126.h| 459 ++
1 file changed, 459 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rv1126.h
diff --git a
Add DDR driver for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
Changes for v2:
- none
.../asm/arch-rockchip/dram_spec_timing.h | 452 +++
.../include/asm/arch-rockchip/sdram_common.h | 212 +
.../include/asm/arch-rockchip/sdram_msch.h| 12
am baseboards
> > for creating complete platform solutions.
> >
> > Add support for it.
> >
> > Sync the i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus
> > from Engicam devicetree file from linux-next tree.
> > commit (arm64: dts: imx8mp: A
On Thu, 1 Sept 2022 at 18:46, Kever Yang wrote:
>
> Hi Jagan,
>
> Does this dtsi already merge in kernel?
Nothing yet. If you apply I can send rebased dts version once Heiko is
picked or will send it to complete the next version once Linux is
merged.
Jagan.
On Fri, 2 Sept 2022 at 08:36, Kever Yang wrote:
>
>
> On 2022/8/18 22:52, Jagan Teki wrote:
> > Rockchip PX30 has 16KB sram, bootrom reserved 4KB as stack.
>
> NAK, the origin code is correct, do not modify this.
SPL size increment due to updating high row detection code -
asted the
> wrong value in my previous email.
Please send a patch to mailinglist, if there is any issue.
Thanks,
Jagan.
-309,6 +310,7 @@ config ROCKCHIP_RK3588
How it related to 3588, couldn't reproduce it from my end at least.
I'm using rk3588_bl31_v1.27.elf from rkbin.
Jagan.
16 MiB erase using 4kiB sector erase opcode 0x20 ... 107.5s
> 16 MiB erase using 64kiB block erase opcode 0xd8 ... 39.1s
> 16 MiB erase using chip erase opcode 0xc7 .. 38.7s
>
> Signed-off-by: Marek Vasut
> ---
Reviewed-by: Jagan Teki
Applied to u-boot-spi/master
On Mon, Mar 27, 2023 at 11:05 AM Kunihiko Hayashi
wrote:
>
> The .supports_op() callback function returns true by default after
> performing driver-specific checks. Therefore the driver cannot apply
> the buswidth in devicetree.
>
> Call spi_mem_default_supports_op() helper to handle the buswidth
On Tue, Mar 7, 2023 at 1:40 PM Jim Liu wrote:
>
> NPCM7xx/NPCM8xx default is boot from flash.
> removed set clock feature due to reliability and security.
> the clock will set by bootblock or tip.
>
> Signed-off-by: Jim Liu
> ---
Reviewed-by: Jagan Teki
Applied to u-boot-spi/master
On Sat, Apr 1, 2023 at 1:04 PM Heinrich Schuchardt
wrote:
>
> Add a missing fallthrough macro to avoid a -Wimplicit-fallthrough warning.
>
> Signed-off-by: Heinrich Schuchardt
> ---
Applied to u-boot-spi/master
On Fri, Apr 7, 2023 at 2:43 PM Ilias Apalodimas
wrote:
>
> When building with clang, the compiler compains with
>
> drivers/spi/spi-synquacer.c:212:11: warning: variable 'bus_width' is used
> uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized]
> else if (priv->mode
--- a/cmd/sf.c
> +++ b/cmd/sf.c
> @@ -353,6 +353,11 @@ static int do_spi_flash_erase(int argc, char *const
> argv[])
> if (ret != 1)
> return CMD_RET_USAGE;
>
> + if (size == 0) {
> + printf("ERROR: Invalid size 0\n");
> + return CMD_RET_FAILURE;
> + }
I feel it is too verbose and if erase happened it shows the log
otherwise it shows nothing, and that is enough.
Jagan.
Linux.
>
> Reviewed-by: Marek Vasut
> Signed-off-by: Takahiro Kuwano
> Signed-off-by: Hai Pham
> Signed-off-by: Cong Dang
> Signed-off-by: Marek Vasut
> ---
Reviewed-by: Jagan Teki
On Wed, Apr 12, 2023 at 4:29 PM Dhruva Gole wrote:
>
> This series aims to address some critical bugs in the cadence qspi
> driver like the need to Flush the CMDCTRL reg after the execution due to
> a hardware limitation and also fixes the check conditions for DTR ops.
>
> previously posted:
> htt
Hi Tom,
Please pull this PR for u-boot-spi.
Summary:
- cadence-quadspi fixes (Apurva Nandan, Dhruva Gole)
- CHIP_ERASE optimization (Marek Vasut)
- fixups for s25fs512s (Takahiro Kuwano)
CI:
https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/16198
The following changes since commit
0x0 0xf400 0x0 0x0010>;
> + reg-names = "dbi", "apb", "config";
> + resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
> + reset-names = "pcie", "periph";
> + rockchip,pipe-grf = <&php_grf>;
> + status = "disabled";
> +
> + pcie2x1l2_intc: legacy-interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = ;
> + };
> + };
Look like we are growing non-linux dt in -u-boot.dtsi. This might not
be a good choice in the long run. I understand the importance of this
SoC but code maintenance must be in a generic way.
Thanks,
Jagan.
ere AHB bus may need to be disabled.
>
> Signed-off-by: Kuldeep Singh
> ---
Acked-by: Jagan Teki
done by IP
> bus and larger length reads using AHB bus. For adding errata workaround,
> use IP bus to read entire flash contents and disable AHB path when
> platform frequency is 300Mhz.
>
> Signed-off-by: Kuldeep Singh
> ---
Reviewed-by: Jagan Teki
On Tue, Mar 23, 2021 at 7:54 AM zhengxun wrote:
>
> The MX66UW2G345G is Macronix Flash with SINGLE and OCTAL I/O. Hence,
> add SPI_NOR_OCTAL_READ flag for this flash.
>
> Signed-off-by: zhengxun
> ---
Applied to u-boot-spi/master
451 insertions(+), 206 deletions(-)
> >
>
> Looks like I forgot to bump the version. This should be v3. I can resend if
> necessary.
Yes, Please.
There are few comments,
1. Patch "spi: spi-mem: Add debug message for spi-mem ops"
As we discussed in the previous version, drop the unnecessary debug
statements after ops execution as this patch trying to add more
verbose to before ops execution.
2. Comments in Patch v2,06/10
Jagan.
p/260789?attachment-id=19522
> https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-MCP-Semper-Flash-with-Quad-SPI/ta-p/260823?attachment-id=29503
>
> Tested on Xilinx Zynq-7000 FPGA board.
Any details about footprint statistics?
Jagan.
On Mon, Apr 19, 2021 at 6:49 PM Sean Anderson wrote:
>
> On 4/19/21 3:06 AM, Jagan Teki wrote:
> > On Sat, Apr 3, 2021 at 4:37 AM Sean Anderson wrote:
> >>
> >> On 4/2/21 7:05 PM, Sean Anderson wrote:
> >>> This series adds support for enhanced SPI
different
behavior, IMHO. Detect the dev number by U-Boot itself and look at
traverse bootenv by all possible dev numbers in sunxi-common.h, but
this has one slide effect that we mark mmc2 as devnum 1 for the sake
of fastboot so if we mark fastboot number for specific board properly
(by static or runtime) then explicit aliases wouldn't required.
Jagan.
On Tue, Apr 20, 2021 at 9:56 AM Takahiro Kuwano wrote:
>
> On 4/19/2021 4:13 PM, Jagan Teki wrote:
> > On Wed, Apr 7, 2021 at 9:01 AM wrote:
> >>
> >> From: Takahiro Kuwano
> >>
> >> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Q
On Mon, Apr 26, 2021 at 4:57 PM Andre Przywara wrote:
>
> On Sun, 25 Apr 2021 18:03:05 +0530
> Jagan Teki wrote:
>
> Hi Jagan,
>
> thanks for your input!
>
> > On Sun, Apr 25, 2021 at 3:30 PM Andre Przywara
> > wrote:
> > >
> > > On Fri,
oC as well.
> Also to make diagnosing this problem easier, print a warning if a board
> tries to setup MMC2 pins without a respective SoC setting being defined.
>
> Signed-off-by: Andre Przywara
> ---
Reviewed-by: Jagan Teki
On Mon, Apr 26, 2021 at 12:30 PM Takahiro Kuwano wrote:
>
> Hi Jagan,
>
> On 4/25/2021 9:42 PM, Jagan Teki wrote:
> > On Tue, Apr 20, 2021 at 9:56 AM Takahiro Kuwano
> > wrote:
> >>
> >> On 4/19/2021 4:13 PM, Jagan Teki wrote:
> >>> On
patch
Changes for v2:
- add Linux commit sha1 in commit messages.
Any inputs?
Jagan.
Jagan Teki (4):
arm64: dts: imx8mm: Add common -u-boot.dtsi
arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM
board: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit
board: imx8mm: Add Engicam i
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