From: Haiying Wang
The original code maps boot flash as non-cacheable region. When calling
relocate_code in flash to copy u-boot from flash to ddr, every loop copy command
is read from flash. The flash read speed will be the bottleneck, which consuming
long time to do this operation. To resovle t
From: Haiying Wang
Enable half drive strength, set RTT to 60Ohm and set write leveling override.
Signed-off-by: Haiying Wang
---
board/freescale/mpc8569mds/ddr.c | 16 +---
1 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/fr
From: Haiying Wang
CONFIG_ENV_SIZE of MPC8569MDS was wrongly set to CONFIG_ENV_SECT_SIZE which
is 128KB, so it took longer time to do crc32 calculation for ENV than it should
do. It causes the bootup for MPC8569MDS significantly slow. This patch fixs it
to 0x2000(8KB), also fix the comment for CO
From: Haiying Wang
The original code maps boot flash as non-cacheable region. When calling
relocate_code in flash to copy u-boot from flash to ddr, every loop copy command
is read from flash. The flash read speed will be the bottleneck, which consuming
long time to do this operation. To resovle t
From: Haiying Wang
Enable half drive strength, set RTT to 60Ohm and set write leveling override.
Signed-off-by: Haiying Wang
---
board/freescale/mpc8569mds/ddr.c | 16 +---
1 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/fr
From: Haiying Wang
CONFIG_ENV_SIZE of MPC8569MDS was wrongly set to CONFIG_ENV_SECT_SIZE which
is 128KB, so it took longer time to do crc32 calculation for ENV than it should
do. It causes the bootup for MPC8569MDS significantly slow. This patch fixs it
to 0x2000(8KB), also fix the comment for CO
From: Haiying Wang
Signed-off-by: Haiying Wang
Acked-by: Scott Wood
---
Makefile | 30 ++
1 files changed, 14 insertions(+), 16 deletions(-)
diff --git a/Makefile b/Makefile
index 5f93646..0d1ea5d 100644
--- a/Makefile
+++ b/Makefile
@@ -287,17 +287,6 @@ LDPPFLA
From: Haiying Wang
Support P1021MDS board to boot from NAND flash (No NOR flash on this
board). And because P1021 only has 256K L2 SRAM, which can not used for final
uboot image, this patch also enables the TPL BOOT on P1021MDS so that DDR can
be initialized in L2 SRAM through SPD code. So there
From: Haiying Wang
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBC
From: Haiying Wang
Signed-off-by: Haiying Wang
---
v3: Use HAS_TPL and IN_TPL, change initdram for TPL, fix the inconsistent
comments.
arch/powerpc/cpu/mpc85xx/cpu.c |7 ++
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 22 ++-
arch/powerpc/cpu/mpc85xx/start.S | 12 ++
From: Haiying Wang
TPL is introduced to enable a loader stub that boots out of some type of RAM,
after being loaded by an SPL or similar platform-specific mechanism.
One example of using this tpl loader is to initialize the ddr through spd code
in case the L2 SRAM size is not big enough to hold
From: Haiying Wang
Signed-off-by: Haiying Wang
---
arch/powerpc/config.mk |4
config.mk |7 ++-
2 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk
index 64191c7..78e53c4 100644
--- a/arch/powerpc/config.m
From: Haiying Wang
Support P1021MDS board to boot from NAND flash (No NOR flash on this
board). And because P1021 only has 256K L2 SRAM, which can not used for final
uboot image, this patch also enables the TPL BOOT on P1021MDS so that DDR can
be initialized in L2 SRAM through SPD code. So there
From: Haiying Wang
commit 8aba9dceebb14144e07d19593111ee3a999c37fc
Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS
breaks the usage of --gc-section to build nand_spl. We still need linker option
--gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes
the --
From: Haiying Wang
Signed-off-by: Haiying Wang
---
arch/powerpc/include/asm/immap_85xx.h |6 ++
arch/powerpc/include/asm/immap_qe.h |9 +++--
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap
From: Haiying Wang
Signed-off-by: Haiying Wang
---
arch/powerpc/cpu/mpc85xx/cpu.c |7 ++
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 22 ++-
arch/powerpc/cpu/mpc85xx/start.S | 12 ++--
arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds | 99 ++
4
From: Haiying Wang
For some board which doesn't have NOR flash and the QE's firmware(ucode) is
saved in its NAND flash, we don't want call qe_init in cpu_init_r, but will
call it later after nand is initialized.
Signed-off-by: Haiying Wang
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +-
1 f
This patchset adds support for TPL(Tertiary Program Loader) and P1021MDS board.
It is a rework of patchset at
http://lists.denx.de/pipermail/u-boot/2010-December/082881.html,
addresses the comments from the list and is based on the top of the tree.
It needs to be applied after patch
http://lists
From: Haiying Wang
Support P1021MDS board to boot from NAND flash (No NOR flash on this
board). And because P1021 only has 256K L2 SRAM, which can not used for final
uboot image, this patch also enables the TPL BOOT on P1021MDS so that DDR can
be initialized in L2 SRAM through SPD code. So there
From: Haiying Wang
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBC
From: Haiying Wang
TPL is introduced to enable a loader stub that boots out of some type of RAM,
after being loaded by an SPL or similar platform-specific mechanism.
One example of using this tpl loader is to initialize the ddr through spd code
in case the L2 SRAM size is not big enough to hold
From: Haiying Wang
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBC
From: Haiying Wang
In the case the QE's microcode is stored in nand flash, we need to load it from
NAND flash to ddr first then the qe_init can get the ucode correctly.
Signed-off-by: Haiying Wang
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +
1 files changed, 17 insertions(
From: Haiying Wang
Signed-off-by: Haiying Wang
---
v2: re-number the res defines in immap_85xx.h, make changes to P1021 specific
defines based on the latest commit in u-boot-85xx git tree.
arch/powerpc/include/asm/config_mpc85xx.h |4
arch/powerpc/include/asm/immap_85xx.h | 24 ++
From: Haiying Wang
commit 8aba9dceebb14144e07d19593111ee3a999c37fc
Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS
breaks the usage of --gc-section to build nand_spl. We still need linker option
--gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes
the --
From: Haiying Wang
commit 8aba9dceebb14144e07d19593111ee3a999c37fc
Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS
breaks the usage of --gc-section to build nand_spl. We still need linker option
--gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes
the --
From: Haiying Wang
Fix u-boot-nand.lds and u-boot-nand_spl.lds according to:
Author: Peter Tyser
Date: Wed Sep 29 14:05:56 2010 -0500
commit fbe53f59bd40b3b1ab66dc98859e26589d64d1b7
85xx: Use gc-sections to reduce image size
Signed-off-by: Haiying Wang
---
arch/powerpc/cpu/mpc85xx/u-bo
From: Haiying Wang
Signed-off-by: Haiying Wang
---
arch/powerpc/cpu/mpc85xx/start.S | 12
include/configs/MPC8536DS.h |8 ++--
include/configs/MPC8569MDS.h | 10 +++---
include/configs/P1_P2_RDB.h |8
From: Haiying Wang
Signed-off-by: Haiying Wang
---
v2 change: remove 8569 CONFIG_MMC change which should not be in this patch.
arch/powerpc/cpu/mpc85xx/start.S | 12
include/configs/MPC8536DS.h |8 ++--
include/configs/MPC8569MDS.h
From: Haiying Wang
Signed-off-by: Haiying Wang
---
v3 change: %s/CONFIG_SYS_TEXT_BASE/CONFIG_SYS_MONITOR_BASE/g
arch/powerpc/cpu/mpc85xx/start.S | 18 +-
include/configs/MPC8536DS.h |8 ++--
include/configs/MPC8569MDS.h |
From: Haiying Wang
This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in
case that the DDR SDRAM is initialized in the 2nd stage uboot and should not
be intialized again in the final stage uboot.
Signed-off-by: Haiying Wang
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |
From: Haiying Wang
Signed-off-by: Haiying Wang
---
arch/powerpc/include/asm/immap_85xx.h |6 ++
arch/powerpc/include/asm/immap_qe.h |9 +++--
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap
From: Haiying Wang
This fixes the compiling error for the board which doesn't have NOR flash
(so CONFIG_FLASH_BASE is not defined)
Signed-off-by: Haiying Wang
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc
From: Haiying Wang
For some board which doesn't have NOR flash and the QE's firmware(ucode) is
saved in its NAND flash, we don't want call qe_init in cpu_init_r, but will
call it later after nand is initialized.
Signed-off-by: Haiying Wang
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +-
1 f
From: Haiying Wang
This patch introduces the third program loader(TPL) to load the final uboot
image after the spl code. Once the CONFIG_SYS_TPL_BOOT is defined,
the CONFIG_TPL_BOOT is enabled to generate the u-boot-tpl.bin. There are two
examples to use tpl:
1. NAND boot. The 4K NAND SPL uboot c
From: Haiying Wang
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBC
From: Haiying Wang
This patch supports P1021MDS board to boot from NAND flash (No NOR flash on this
board). And because P1021 only has 256K L2 SRAM, can not used for final uboot
image, this patch defines the CONFIG_SYS_TPL_BOOT for P1021MDS so that DDR can
be initialized in L2 SRAM through SPD co
From: Haiying Wang
TPL is introduced to enable a loader stub that boots out of some type of RAM,
after being loaded by an SPL or similar platform-specific mechanism.
One example of using this tpl loader is to initialize the ddr through spd code
in case the L2 SRAM size is not big enough to hold
From: Haiying Wang
This fixes the compiling error for the board which doesn't have NOR flash
(so CONFIG_FLASH_BASE is not defined)
Signed-off-by: Haiying Wang
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc
This is the second version of patchset to add support of TPL(Tertiary Program
Loader) and P1021MDS board. Compared with the previous version, patch #3 is
splitted into two patches and incorporates the comments from Wolfgang and Mike.
Patch#4 has changes based on 2010.12-rc2 release. The other pat
From: Haiying Wang
This patch adds fsl_ddr_sdram_size to only calculate the ddr sdram size, in
case that the DDR SDRAM is initialized in the 2nd stage uboot and should not
be intialized again in the final stage uboot.
Signed-off-by: Haiying Wang
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |
From: Haiying Wang
TPL is introduced to enable a loader stub that boots out of some type of RAM,
after being loaded by an SPL or similar platform-specific mechanism.
One example of using this tpl loader is to initialize the ddr through spd code
in case the L2 SRAM size is not big enough to hold
From: Haiying Wang
Signed-off-by: Haiying Wang
---
Splitted from TPL patch to only address 85xx changes
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 34 ++-
arch/powerpc/cpu/mpc85xx/start.S | 12 ++--
arch/powerpc/cpu/mpc85xx/u-boot-tpl.lds | 99
From: Haiying Wang
Signed-off-by: Haiying Wang
---
arch/powerpc/include/asm/immap_85xx.h |6 ++
arch/powerpc/include/asm/immap_qe.h |9 +++--
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap
From: Haiying Wang
For some board which doesn't have NOR flash and the QE's firmware(ucode) is
saved in its NAND flash, we don't want call qe_init in cpu_init_r, but will
call it later after nand is initialized.
Signed-off-by: Haiying Wang
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +-
1 f
From: Haiying Wang
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBC
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