Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
doc/README.mpc8572ds | 167 ++
1 files changed, 167 insertions(+), 0 deletions(-)
create mode 100644 doc/README.mpc8572ds
diff --git a/doc/README.mpc8572ds b/doc/README.mpc8572ds
new fil
it is not a valid
value for second core which runs kernel at different physical address other
than 0x0.
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
cpu/mpc85xx/release.S |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/rel
This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS,
and prints each CPU's frequency separately. It also fixes up each CPU's
frequency in "clock-frequency" of fdt blob.
Signed-off-by: James Yang <[EMAIL PROTECTED]>
Signed-off-by: Haiying Wang <
This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS,
and prints each CPU's frequency separately. It also fixes up each CPU's
frequency in "clock-frequency" of fdt blob.
Signed-off-by: James Yang <[EMAIL PROTECTED]>
Signed-off-by: Haiying Wang <
MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1
according to the board spec, and adds the 2nd i2c bus offset.
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
include/configs/MPC8572DS.h |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
include/configs/MPC8536DS.h |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 2578bef..0ecf2a2 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/c
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set base_address and total memory for each ddr controller in memory
controller interleaving mode.
Signed-off-by: Haiying Wang <[EMAIL PROTEC
Current new DDR code has included DDR interleaving support but has not
been tested out. The following patches fix the bugs for common code,
enable run time configuration of memory controller interleaving mode and
bank interleaving mode and add board specific parameters table to
decides the ddr cont
/cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
board/atum8548/ddr.c |5 ++-
board/freescale/mpc
* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
ba_intlv_ctl.
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
cpu/mpc8xxx/ddr/main.c
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 6297141..1783e92 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++
) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.
* Change CONFIG_ICS307_REFCLK_HZ from to 3000.
Signed-off-by: James Yang <[EMAIL PROTECTED]>
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
board/freescale/mpc8572ds/
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay based on board ddr frequency and n_ranks.
* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
Signed-off-by: James Yang <[EMAIL PROTECTED]>
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set base_address and total memory for each ddr controller in memory
controller interleaving mode.
Signed-off-by: Haiying Wang <[EMAIL PROTEC
/cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
board/atum8548/ddr.c |5 ++-
board/freescale/mpc
* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
ba_intlv_ctl.
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
cpu/mpc8xxx/ddr/main.c
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 6297141..1783e92 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++
) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.
* Change CONFIG_ICS307_REFCLK_HZ from to 3000.
Signed-off-by: James Yang <[EMAIL PROTECTED]>
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
board/freescale/mpc8572ds/
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay based on board ddr frequency and n_ranks.
* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
Signed-off-by: James Yang <[EMAIL PROTECTED]>
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
On Sat, 2008-10-04 at 01:35 +0200, Wolfgang Denk wrote:
> Dear Haiying Wang,
>
> In message <[EMAIL PROTECTED]> you wrote:
> > Fix some bugs:
> > 1. Correctly set intlv_ctl in cs_config.
> > 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is e
, and adds the 2nd i2c bus offset.
> >
> > Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
>
> I see "[PATCH 1/3] Minor fixes for I2C address on MPC8572DS" and
> "[PATCH 3/3] Remove redundant #define for MPC8536DS".
>
> I cannot see a "[PATCH 2/3]&
The ID EEPROM on MPC8572DS board locates on I2C bus 1. Its the storage for
system information like mac addresses etc. This patch enables it.
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
include/configs/MPC8572DS.h | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
The patchset supports SRAM boot, P1021MDS NAND boot, P1021MDS QE/UEC, it
is against the git://git.denx.de/u-boot-mpc85xx.
Thanks.
Haiying
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introduced by commit cc9f607beb49d4d3556c326efb83a0a51784e484, it causes:
"
cmd_mmc.c:136:2: warning: missing terminating " character
cmd_mmc.c:133: error: missing terminating " character
make[1]: *** [cmd_mmc.o] Error 1
"
Signed-off-by: Haiying Wang
---
common/cmd_mmc.
On Mon, 2010-16-08 at 07:42 +0200, Wolfgang Denk wrote:
> Dear Haiying Wang,
> Please keep in mind that patches shall be submitted against the
> mainline repository, NOPT against any custodian branches.
> This is to make sure everybody can apply and test these without
> addinitiona
so it can be called in other file.
Signed-off-by: Haiying Wang
---
nand_spl/nand_boot_fsl_elbc.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c
index 9547d44..efac293 100644
--- a/nand_spl
es to keep the sram uboot
size as
small as possible.
Signed-off-by: Haiying Wang
---
Makefile | 18 ++-
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c | 31 +++-
arch/powerpc/cpu/mpc85xx/sram_boot/Makefile| 190
arch/p
This fixes the compiling error for the board which doesn't have NOR flash
(so CONFIG_FLASH_BASE is not defined)
Signed-off-by: Haiying Wang
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init
This patch supports P1021MDS NAND boot with the following features:
* Boot from NAND flash with SRAM BOOT support.(No NOR flash on this board)
* SPD DDR Initialization
Signed-off-by: Haiying Wang
Signed-off-by: Mohit Kumar
Signed-off-by: Yu.Liu
---
MAKEALL
Signed-off-by: Haiying Wang
---
arch/powerpc/include/asm/immap_85xx.h |6 ++
arch/powerpc/include/asm/immap_qe.h |7 ++-
2 files changed, 12 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index c1382c8
and because some platforms need to load QE firmware from NAND flash(no NOR
flash), it makes qe_init to be called after nand_init.
Signed-off-by: Haiying Wang
---
arch/powerpc/cpu/mpc83xx/cpu_init.c |8
arch/powerpc/cpu/mpc85xx/cpu_init.c |8
arch/powerpc/lib/board.c
-off-by: Haiying Wang
---
arch/powerpc/cpu/mpc85xx/speed.c |4 ++
arch/powerpc/include/asm/immap_85xx.h | 13
board/freescale/p1021mds/p1021mds.c | 54 +
drivers/qe/uec.c | 36 ++
include/configs
On Mon, 2010-16-08 at 12:11 +0200, Wolfgang Denk wrote:
> >
> > diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
> > b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> > index 2c3be6d..1fbc0cc 100644
> > --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
> > +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
> > @@ -327,7 +3
On Mon, 2010-16-08 at 12:09 +0200, Wolfgang Denk wrote:
> Dear Haiying Wang,
>
> In message <1281945721.24612.11.ca...@localhost.localdomain> you wrote:
> > so it can be called in other file.
> >
> > Signed-off-by: Haiying Wang
> > ---
> > nand_sp
On Mon, 2010-16-08 at 12:23 +0200, Wolfgang Denk wrote:
> Dear Haiying Wang,
>
> In message <1281945897.24612.17.ca...@localhost.localdomain> you wrote:
> > Once CONFIG_MIDDLE_STAGE_SRAM_BOOT is defined, CONFIG_SRAM_BOOT is enabled
> > to
> > generate u-boot-sra
On Mon, 2010-16-08 at 12:33 +0200, Wolfgang Denk wrote:
> > --- /dev/null
> > +++ b/board/freescale/p1021mds/bcsr.h
> > @@ -0,0 +1,18 @@
> > +/*
> > + * Copyright (C) 2010 Freescale Semiconductor, Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * u
On Mon, 2010-16-08 at 12:40 +0200, Wolfgang Denk wrote:
> Dear Haiying Wang,
>
> In message <1281947090.24612.23.ca...@localhost.localdomain> you wrote:
> > and because some platforms need to load QE firmware from NAND flash(no NOR
> > flash), it makes qe_init t
On Wed, 2010-29-09 at 20:25 +0200, Wolfgang Denk wrote:
> You submitted the same patch series twice, without any version ID in
> the subject, and without any other indication about possible changes.
I am so sorry for sending the patchset twice. I did not add
"smtp-server" at the first time, then I
On Sat, 2011-01-22 at 23:12 +0100, Wolfgang Denk wrote:
> You should not undo a previous copyright. I guess you mean:
>
> Copyright 2009-2010 Freescale Semiconductor, Inc.
>
> ?
Yes. Sorry about it.
> > +DECLARE_GLOBAL_DATA_PTR;
>
> Please move this up to top of file.
OK.
> > +unsigned lon
On Sat, 2011-01-22 at 23:04 +0100, Wolfgang Denk wrote:
> > diff --git a/Makefile b/Makefile
> > index 87a383d..94af465 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -290,6 +290,10 @@ LDPPFLAGS += \
> > $(shell $(LD) --version | \
> > sed -ne 's/GNU ld version
> > \([0-9][0-9]*\)\.
On Mon, 2011-01-24 at 13:49 +0100, Wolfgang Denk wrote:
> > > >
> > > > +ifeq ($(CONFIG_TPL_U_BOOT),y)
> > > > +TPL_BOOT = tpl
> > > > +endif
> > >
> > > I don't understand what the "TPL_BOOT" is good for, or how it's
> > > supposed to work.
> > TPL_BOOT works like NAND_SPL but after NAND_SPL is
On Mon, 2011-01-24 at 23:09 +0100, Wolfgang Denk wrote:
> Dear Haiying Wang,
>
> In message <1295906076.2051.127.camel@haiying-laptop> you wrote:
> >
> > > What I do not understand is what the TPL_BOOT variable in the
> > > Makefile is good for. I cannot un
Dear Wolfgang,
On Mon, 2011-01-24 at 23:29 +0100, Wolfgang Denk wrote:
> Dear Haiying Wang,
>
> In message <1295907459.2051.158.camel@haiying-laptop> you wrote:
> >
> > > It's not the name. But you use it ina few places here, buth then hard
> > > e
On Fri, 2011-01-28 at 11:02 +0100, Fabian Cenedese wrote:
>
> I'm not questioning the patch, I'm just trying to understand.
>
> >+#define CONFIG_MP /* Multiprocessor support */
> >+
> >+#define CONFIG_PCI /* Disable PCI/PCIE */
>
> Shouldn't that be "Enab
On Fri, 2011-01-28 at 08:49 -0600, Kumar Gala wrote:
> > +
> > +struct law_entry law_table[] = {
> > +#ifndef CONFIG_IN_TPL
> > + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
> > + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
> > + SET_LAW(CON
On Fri, 2011-01-28 at 11:36 -0600, Scott Wood wrote:
> On Thu, 27 Jan 2011 23:58:10 -0500
> wrote:
>
> > From: Haiying Wang
> >
> > Signed-off-by: Haiying Wang
> > ---
> > arch/powerpc/config.mk |4
> > config.mk |7
On Fri, 2011-01-28 at 12:30 -0600, Scott Wood wrote:
> > > > diff --git a/config.mk b/config.mk
> > > > index 5147c35..d7bb07f 100644
> > > > --- a/config.mk
> > > > +++ b/config.mk
> > > > @@ -260,8 +260,13 @@ $(obj)%.s: %.c
> > > >
> > > > ###
On Fri, 2011-01-28 at 13:46 -0500, Haiying Wang wrote:
> > In any case, I don't think we want different behavior here based on
> > whether we have TPL. Either LDFLAGS is used in partial linking, or
> > it's not.
> I don't understand why LDFLAGS was added
On Fri, 2011-01-28 at 13:06 -0600, Timur Tabi wrote:
> On Thu, Jan 27, 2011 at 10:58 PM, wrote:
>
> > +/* These are used when DDR doesn't use SPD. */
> > +#define CONFIG_SYS_SDRAM_SIZE 512/* DDR is 512MB */
> > +#define CONFIG_SYS_DDR_CS0_BNDS 0x001F
> > +#defi
On Fri, 2011-01-28 at 13:24 -0600, Timur Tabi wrote:
> Haiying Wang wrote:
> >>> +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
> >> >
> >> > Not 0x57? That's where the NXID EEPROM almost always is.
> > It is board specific value, isn't i
On Mon, 2011-01-31 at 20:33 +0100, Wolfgang Denk wrote:
> If I understand the intention of the LDFLAGS_u-boot setting
> corrrectly, then you would have to add a "LDFLAGS_nand_spl" setting.
No, I don't want to add a LDFLAGS_nand_spl for nand_spl only, I need
LDFLAGS_FINAL to be passed to nand spl,
On Mon, 2011-01-31 at 21:11 +0100, Wolfgang Denk wrote:
> >
> > +#ifdef CONFIG_P1021
> > + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> > +
> > + /* QE9 and QE12 need to be set for enabling QE MII managment signals */
> > + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
> >
On Mon, 2011-01-31 at 21:08 +0100, Wolfgang Denk wrote:
> Dear haiying.w...@freescale.com,
>
> In message <1296499317-26616-6-git-send-email-haiying.w...@freescale.com> you
> wrote:
> > From: Haiying Wang
> >
> > For some board which doesn't have
On Mon, 2011-01-31 at 21:03 +0100, Wolfgang Denk wrote:
> Dear haiying.w...@freescale.com,
> > diff --git a/board/freescale/p1021mds/config.mk
> > b/board/freescale/p1021mds/config.mk
> > new file mode 100644
> > index 000..3888f61
> > --- /dev/null
> > +++ b/board/freescale/p1021mds/config.mk
On Mon, 2011-01-31 at 15:28 -0600, Kumar Gala wrote:
> On Jan 31, 2011, at 2:50 PM, Haiying Wang wrote:
>
> > On Mon, 2011-01-31 at 21:11 +0100, Wolfgang Denk wrote:
> >>>
> >>> +#ifdef CONFIG_P1021
> >>> + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC
On Tue, 2011-02-01 at 08:34 +0100, Wolfgang Denk wrote:
> Can you please be more specific? I don't see where "the
> LDFLAGS_u-boot commit" (you mean 8aba9dc ?) would change any related
> code. The relevant hunk looks like this:
>
> @@ -204,9 +204,11 @@ endif
>
> AFLAGS := $(AFLAGS_DEBUG) -D_
On Tue, 2011-02-01 at 10:50 -0600, Scott Wood wrote:
> > >
> > If it is a one time setting, there should be no problem to put it into
> > board code. But these pin settings need to be done before any usage of
> > phy read/write (accessing MDIO/MDC), and need to be released after the
> > usage of p
On Tue, 2011-02-01 at 13:15 -0600, Kumar Gala wrote:
> On Feb 1, 2011, at 11:01 AM, Haiying Wang wrote:
>
> > On Tue, 2011-02-01 at 10:50 -0600, Scott Wood wrote:
> >>>>
> >>> If it is a one time setting, there should be no problem to put it into
> >
On Wed, 2011-02-02 at 11:27 -0600, Kumar Gala wrote:
> +void cpu_late_init_r(void)
> +{
> +#ifdef CONFIG_QE
> + uint qe_base = CONFIG_SYS_IMMR + 0x0008; /* QE immr base */
> + qe_init(qe_base);
> + qe_reset();
> +#endif
> +}
You did not move qe_reset() inside qe_init() as you recomm
Dear Wolfgang,
On Thu, 2011-01-27 at 09:44 -0500, haiying.w...@freescale.com wrote:
> From: Haiying Wang
>
> Signed-off-by: Haiying Wang
> Acked-by: Scott Wood
>
> ---
> Makefile | 30 ++
> 1 files changed, 14 insertions(+), 16 deleti
Dear Wolfgang,
On Tue, 2011-02-01 at 14:40 -0600, Scott Wood wrote:
> On Tue, 1 Feb 2011 21:20:50 +0100
> Wolfgang Denk wrote:
>
> > Dear Scott Wood,
> >
> > In message <20110201135136.0817f...@udp111988uds.am.freescale.net> you
> > wrote:
> > >
> > > > > Prior to the introduction of LDFLAGS_
On Wed, 2011-05-04 at 22:53 +0530, Poonam Aggrwal wrote:
> +sinclude $(obj).depend
> +
> +#
> diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c
> b/nand_spl/board/freescale/p1010rdb/nand_boot.c
> new file mode 100644
On Wed, 2011-05-04 at 12:34 -0500, Kumar Gala wrote:
> >> +
> >> +#define udelay(x) {int i, j; for (i = 0; i < x; i++) for (j = 0; j <
> >> 1; j++); }
> > There were many comments on this udelay before, we should not use this
> > define, but use the udelay() which u-boot provides.
> >
>
> Is
For the silicon which doesn't have ROM support in QE, it always needs to load
a pre-built ucode binary to IRAM so that QE can work.
Signed-off-by: Haiying Wang
Signed-off-by: Hillel Avni
---
drivers/qe/qe.c |9 +
drivers/qe/qe.h |1 +
2 files changed, 10 insertions(
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR
in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then
invalidate it after LBCR bit 13 is set.
Signed-off-by: Haiying Wang
---
cpu/mpc85xx/Makefile |1 +
cpu/mpc85xx/cpu.c
This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD
EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch.
Signed-off-by: Haiying Wang
Signed-off-by: Hillel Avni
---
MAKEALL |1 +
Makefile
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR
in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then
invalidate it after LBCR bit 13 is set.
Signed-off-by: Haiying Wang
---
cpu/mpc85xx/Makefile |1 +
cpu/mpc85xx/cpu.c
This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD
EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch.
Signed-off-by: Haiying Wang
Signed-off-by: Hillel Avni
---
MAKEALL |1 +
Makefile
Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
define MAX_QE_RISC for QE based silicons.
Signed-off-by: Haiying Wang
---
drivers/qe/qe.c|3 ---
drivers/qe/qe.h| 15 ++-
drivers/qe/uec.c | 30
MPC8569MDS board needs more memory for malloc because it will support four
Ethernet interfaces.
Signed-off-by: Haiying Wang
---
include/configs/MPC8569MDS.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
Signed-off-by: Haiying Wang
Signed-off-by: Yu Liu
---
include/configs/MPC8569MDS.h | 10 +-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index b0af5dc..2cba98f 100644
--- a/include/configs/MPC8569MDS.h
+++ b
Signed-off-by: Haiying Wang
---
cpu/mpc85xx/cpu.c|4
cpu/mpc85xx/speed.c | 13 +
include/asm-ppc/immap_85xx.h |2 ++
include/e500.h |1 +
4 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu
Signed-off-by: Haiying Wang
---
board/freescale/mpc8569mds/bcsr.c |4
board/freescale/mpc8569mds/mpc8569mds.c | 30 ++
include/configs/MPC8569MDS.h| 23 +++
3 files changed, 57 insertions(+), 0 deletions(-)
diff
MPC8569 UART1 signals are muxed with PortF bit[9-12], we need to define
those pins before using UART1.
Signed-off-by: Haiying Wang
---
board/freescale/mpc8569mds/mpc8569mds.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c
b
MPC8569 has 128K bytes MURAM.
Signed-off-by: Haiying Wang
---
include/asm-ppc/immap_qe.h |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index 9530b29..7613b5c 100644
--- a/include/asm-ppc/immap_qe.h
+++ b
This patch supports UCC working at RMII mode on PIB board, fixup fdt blob to
support rmii in kernel. It also changes the name of enable_mpc8569mds_qe_mdio to
enalbe_mpc8569mds_qe_uec which is more accurate.
Signed-off-by: Haiying Wang
---
board/freescale/mpc8569mds/bcsr.c | 15
Some QE chips like 8569 need more SNUM numbers for supporting 4 UECs in RGMII-
1000 mode.
Signed-off-by: Haiying Wang
---
drivers/qe/qe.c| 13 +++--
drivers/qe/qe.h|1 -
include/asm-ppc/immap_qe.h |3 +++
3 files changed, 14 insertions(+), 3 deletions
Signed-off-by: Haiying Wang
Acked-by: Timur Tabi
---
v2 change: Fix the indention issue pointed by Scott, and add Acked-by.
cpu/mpc85xx/cpu.c|4
cpu/mpc85xx/speed.c | 13 +
include/asm-ppc/immap_85xx.h |2 ++
include/e500.h |1
Signed-off-by: Haiying Wang
---
board/freescale/mpc8569mds/bcsr.c |4
board/freescale/mpc8569mds/mpc8569mds.c | 30 ++
include/configs/MPC8569MDS.h| 23 +++
3 files changed, 57 insertions(+), 0 deletions(-)
diff
From: Dave Liu
The BCSR17[7] = 1 will unlock the write protect of FLASH.
The WP# pin only controls the write protect of top/bottom sector,
That is why we can save env, but we can't write the first sector
before the patch.
Signed-off-by: Dave Liu
Signed-off-by: Haiying Wang
---
MPC8569 has 128K bytes MURAM.
Signed-off-by: Haiying Wang
---
include/asm-ppc/immap_qe.h |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index 66a4735..55667ca 100644
--- a/include/asm-ppc/immap_qe.h
+++ b
thus the saved environment variables
will not be erased after u-boot is re-programmed.
Signed-off-by: Haiying Wang
Signed-off-by: Dave Liu
---
include/configs/MPC8569MDS.h | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/configs/MPC8569MDS.h b/include/co
Some QE chips like 8569 need more SNUM numbers for supporting 4 UECs in RGMII-
1000 mode.
Signed-off-by: Haiying Wang
Acked-by: Timur Tabi
---
drivers/qe/qe.c| 15 ---
drivers/qe/qe.h|1 -
include/asm-ppc/immap_qe.h |5 -
3 files changed, 16
MPC8569 UART1 signals are muxed with PortF bit[9-12], we need to define
those pins before using UART1.
Signed-off-by: Haiying Wang
---
board/freescale/mpc8569mds/mpc8569mds.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c
b
Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
define MAX_QE_RISC for QE based silicons.
Signed-off-by: Haiying Wang
Acked-by: Timur Tabi
---
drivers/qe/qe.c|3 ---
drivers/qe/qe.h| 17 +++--
drivers/qe/uec.c
Signed-off-by: Haiying Wang
---
drivers/qe/uec.c | 17 +
drivers/qe/uec.h | 31 +--
2 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index deeb947..7649f9f 100644
--- a/drivers/qe/uec.c
+++ b
Here is the patchset for adding new features for QE UEC and MPC8569MDS
board. Please review this patchset and ignore the one(9 patches) I sent
out some weeks ago, since there are some update in the new patches.
Thanks.
Haiying
___
U-Boot mailing list
This patch supports UCC working at RMII mode on PIB board, fixup fdt blob to
support rmii in kernel. It also changes the name of enable_mpc8569mds_qe_mdio to
enalbe_mpc8569mds_qe_uec which is more accurate.
Signed-off-by: Haiying Wang
---
board/freescale/mpc8569mds/bcsr.c | 15
Signed-off-by: Haiying Wang
---
cpu/mpc85xx/cpu.c |6 +
cpu/mpc85xx/fdt.c |4 ++-
drivers/qe/uec.c | 66 -
3 files changed, 74 insertions(+), 2 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index b812d88
Signed-off-by: Haiying Wang
Signed-off-by: Yu Liu
---
include/configs/MPC8569MDS.h | 10 +-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index ea996ff..c87e51d 100644
--- a/include/configs/MPC8569MDS.h
+++ b
Signed-off-by: Haiying Wang
Acked-by: Timur Tabi
---
cpu/mpc85xx/cpu.c|4
cpu/mpc85xx/speed.c | 15 ++-
include/asm-ppc/immap_85xx.h |2 ++
include/e500.h |1 +
4 files changed, 21 insertions(+), 1 deletions(-)
diff --git a/cpu
On MPC8569MDS board, UCC6 and UCC8 can be configured to work at SGMII mode via
UEM on PB board. Since MPC8569 supports up to 4 Gigabit Ethernet ports, we
disable UEC6 and UEC8 by default.
Signed-off-by: Haiying Wang
---
include/configs/MPC8569MDS.h | 25 +
1 files
Signed-off-by: Haiying Wang
---
doc/README.mpc8569mds | 78 +
1 files changed, 78 insertions(+), 0 deletions(-)
create mode 100644 doc/README.mpc8569mds
diff --git a/doc/README.mpc8569mds b/doc/README.mpc8569mds
new file mode 100644
index
We support up to 8 mac addresses in system eeprom, so we'd limit the mac_count
to 8, and update the number of ethxaddr if there is more than 4 ethernet ports.
Signed-off-by: Haiying Wang
---
board/freescale/common/sys_eeprom.c | 11 +--
1 files changed, 9 insertions(+), 2 dele
Rename riscRx/riscTx to risc_rx/risc_tx to comply with Codingstyle.
Signed-off-by: Haiying Wang
---
This patch should be applied before the 15 patches I sent out yesterday
drivers/qe/uec.c | 32
drivers/qe/uec.h |4 ++--
2 files changed, 18 insertions
Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
define MAX_QE_RISC for QE based silicons.
Signed-off-by: Haiying Wang
Acked-by: Timur Tabi
---
v2 change: rename riscRx and riscTx to risc_rx and risc_tx
drivers/qe/qe.c|3 ---
drivers/qe/qe.h
We support up to 8 mac addresses in system eeprom, so we define the macro
MAX_NUM_PORTS to limit the mac_count to 8, and update the number of ethxaddr
according to mac_count.
Signed-off-by: Haiying Wang
---
v2 change: define MAC_NUM_PORTS to limit the mac_count
board/freescale/common
We support up to 8 mac addresses in system eeprom, so we define the macro
MAX_NUM_PORTS to limit the mac_count to 8, and update the number of ethxaddr
according to mac_count.
Signed-off-by: Haiying Wang
---
v3 change: Modify printf info and replace 8 with MAX_NUM_PORTS for array mac[]
board
- Increase the size of malloc to 512KB because MPC8569MDS needs more memory for
malloc to support up to eight Ethernet interfaces.
- Move Environment address out of uboot thus the saved environment variables
will not be erased after u-boot is re-programmed.
Signed-off-by: Haiying Wang
---
v2
We support up to 8 mac addresses in system eeprom, so we define the macro
MAX_NUM_PORTS to limit the mac_count to 8, and update the number of ethxaddr
according to mac_count.
Signed-off-by: Haiying Wang
---
v4 change: white space clean up
board/freescale/common/sys_eeprom.c | 23
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