[U-Boot] [PATCH 1/1] imx6: fix random hang when download by usb

ROM did not invalidate L1 cache when download by usb Need invalidate L1 cache before enable cache Signed-off-by: Huang yongcai Signed-off-by: Frank Li --- arch/arm/cpu/armv7/mx6/soc.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch

[U-Boot] [PATCH 1/1] imx6: fix random hang when download by mfgtools

ROM did not invalidate L1 cache when download by usb Need invalidate L1 cache before enable cache Signed-off-by: Huang yongcai Signed-off-by: Frank Li --- arch/arm/cpu/armv7/mx6/soc.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch

[U-Boot] [PATCH 2/3] mx7: psci: add basic psci support

add basic psci support for imx7 chip. support cpu_on and cpu_off. linux kernel boot at nosecure mode. set csu allow nosecure mode kernel to access all peripherial register Signed-off-by: Frank Li --- arch/arm/cpu/armv7/mx7/Makefile | 4 ++ arch/arm/cpu/armv7/mx7/psci-mx7.c | 79

[U-Boot] [PATCH 1/3] ARM: relocate: fix hang when CONFIG_ARMV7_SECURE_BASE

When added above configuration, iram fix up plus relocate offset may locate in invalidate space. Write back fix up value will cause data abort. Add address check, skip psci code. Signed-off-by: Frank Li --- arch/arm/lib/relocate.S | 4 1 file changed, 4 insertions(+) diff --git a/arch

[U-Boot] [PATCH 3/3] imx: config: default enable nosec mode

Enable psci and nosec linux boot. So second core can boot at community 4.13 kernel. Signed-off-by: Frank Li --- include/configs/mx7_common.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index ea2be49..3231d26 100644

Re: [U-Boot] Booting MX6 via Serial Download after DM conversion

Li ; Otavio Salvador > ; Breno Matheus Lima ; > Frank Li > Subject: RE: Booting MX6 via Serial Download after DM conversion > > > > Subject: Re: Booting MX6 via Serial Download after DM conversion > > > > Hi Peng, > > > > On Thu, Apr 25, 2019 at 4:

Re: [PATCH 01/10] dt-bindings: i3c: Add YAML schema for Cadence I3C controller

On Tue, Feb 18, 2025 at 10:56:56AM +0800, dinesh.mani...@intel.com wrote: > From: Dinesh Maniyam > > Add a YAML device tree binding schema for the Cadence I3C controller, Cadence or snps? compatible string said snps. > defining required and optional properties for proper integration > and valida