[PATCH 0/2] add a trailing space to prompt for visionfive2 board

Adds a trailing space to SYS_PROMPT to make it easier to distinguish between commands and the prompt. Chanho Park (2): configs: visionfive2: add a trailing space to prompt doc: visionfive2: apply a trailing space to the prompt configs/starfive_visionfive2_defconfig | 2 +- doc/board

[PATCH 2/2] doc: visionfive2: apply a trailing space to the prompt

Apply the trailing space changes in the guide document. Signed-off-by: Chanho Park --- doc/board/starfive/visionfive2.rst | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst index

[PATCH 1/2] configs: visionfive2: add a trailing space to prompt

Adds a trailing space to SYS_PROMPT to make it easier to distinguish between commands and the prompt. Signed-off-by: Chanho Park --- configs/starfive_visionfive2_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/starfive_visionfive2_defconfig b/configs

RE: [RFC 1/1] rng: Provide a RNG based on the RISC-V Zkr ISA extension

ed-off-by: Heinrich Schuchardt This works fine on my qemu risv with your opensbi patch and KASLR has been tested as well. Feel free to add my reviewed/tested-by tag. Reviewed-by: Chanho Park Tested-by: Chanho Park Best Regards, Chanho Park > --- > drivers/rng/Kconfig | 11 +

[PATCH 2/5] clk: starfive: jh7110: Add security clocks

Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG device. Signed-off-by: Chanho Park --- drivers/clk/starfive/clk-jh7110.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 31aaf3340f94

[PATCH 4/5] riscv: dts: jh7110: Add rng device tree node

Adds jh7110 trng device tree node. Signed-off-by: Chanho Park --- arch/riscv/dts/jh7110.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index ec237a46ffba..13c47f7caa36 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b

[PATCH 0/5] Add support for StarFive JH7110 TRNG driver

pport 128-bit and 256-bit random number generation but this patch makes 256-bit default mode for convenience. Chanho Park (5): riscv: import read/write_relaxed functions clk: starfive: jh7110: Add security clocks rng: Add StarFive JH7110 RNG driver riscv: dts: jh7110: Add rng device tree

[PATCH 5/5] configs: visionfive2: Enable JH7110 RNG driver

Enables JH7110 RNG driver to visionfive2 board. Signed-off-by: Chanho Park --- configs/starfive_visionfive2_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index b21754feafce..b15e7d24db19 100644

[PATCH 1/5] riscv: import read/write_relaxed functions

This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h to use read/write[b|w|l|q]_relaxed functions. Signed-off-by: Chanho Park --- arch/riscv/include/asm/io.h | 45 + 1 file changed, 45 insertions(+) diff --git a/arch/riscv/include/asm

[PATCH 3/5] rng: Add StarFive JH7110 RNG driver

Adds to support JH7110 TRNG driver which is based on linux kernel's jh7110-trng.c. This can support to generate 256-bit random numbers and 128-bit but this makes 256-bit default for convenience. Signed-off-by: Chanho Park --- drivers/rng/Kconfig | 6 + drivers/rng/Makefile

[PATCH 1/2] riscv: cpu: jh7110: Add gpio helper macros

Add gpio.h header file that includes JH7110 helper macros. The file is imported from StarFive github[1] with small changes such as alignment. [1]: https://github.com/starfive-tech/u-boot Signed-off-by: Chanho Park --- arch/riscv/include/asm/arch-jh7110/gpio.h | 85 +++ 1

[PATCH 2/2] board: starfive: spl: Support jtag for VisionFive2 board

/ Output Signed-off-by: Chanho Park --- board/starfive/visionfive2/spl.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index ad5f71a20180..336f0cdfc90f 100644 --- a/board/starfive/visionfive2/spl.c +++ b

[PATCH 0/2] Support JTAG for VisionFive2 board

To support JTAG for VisionFive2 board, we need to control JTAG pins by S/W. spl_board_init_f function seems to be proper place to initialize these pins. Chanho Park (2): riscv: cpu: jh7110: Add gpio helper macros board: starfive: spl: Support jtag for VisionFive2 board arch/riscv/include

RE: [PATCH 3/5] rng: Add StarFive JH7110 RNG driver

> -Original Message- > From: Heinrich Schuchardt > Sent: Wednesday, November 1, 2023 6:18 AM > To: Chanho Park > Cc: Sughosh Ganu ; Rick Chen ; > Leo ; u-boot@lists.denx.de > Subject: Re: [PATCH 3/5] rng: Add StarFive JH7110 RNG driver > > On 10/30/23 09:32,

[PATCH v2 0/5] Add support for StarFive JH7110 TRNG driver

pport 128-bit and 256-bit random number generation but this patch makes 256-bit default mode for convenience. Changes from v1: - Patch #3: Apply Heinrich's reviews and his codes - Patch #5: Add Heinrich's R-b tag Chanho Park (5): riscv: import read/write_relaxed functions clk: starfi

[PATCH v2 2/5] clk: starfive: jh7110: Add security clocks

Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG device. Signed-off-by: Chanho Park --- drivers/clk/starfive/clk-jh7110.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 31aaf3340f94

[PATCH v2 4/5] riscv: dts: jh7110: Add rng device tree node

Adds jh7110 trng device tree node. Signed-off-by: Chanho Park --- arch/riscv/dts/jh7110.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index ec237a46ffba..13c47f7caa36 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b

[PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver

Adds to support JH7110 TRNG driver which is based on linux kernel's jh7110-trng.c. This can support to generate 256-bit random numbers and 128-bit but this makes 256-bit default for convenience. Signed-off-by: Chanho Park --- drivers/rng/Kconfig | 6 + drivers/rng/Makefile

[PATCH v2 5/5] configs: visionfive2: Enable JH7110 RNG driver

Enables JH7110 RNG driver to visionfive2 board. Signed-off-by: Chanho Park Reviewed-by: Heinrich Schuchardt --- configs/starfive_visionfive2_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index

[PATCH v2 1/5] riscv: import read/write_relaxed functions

This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h to use read/write[b|w|l|q]_relaxed functions. Signed-off-by: Chanho Park --- arch/riscv/include/asm/io.h | 45 + 1 file changed, 45 insertions(+) diff --git a/arch/riscv/include/asm

RE: [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver

> -Original Message- > From: Jaehoon Chung > Sent: Wednesday, November 1, 2023 9:52 AM > To: 'Chanho Park' ; 'Sughosh Ganu' > ; 'Heinrich Schuchardt' ; > 'Rick Chen' ; 'Leo' ; u- > b...@lists.de

[PATCH v3 1/5] riscv: import read/write_relaxed functions

This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h to use read/write[b|w|l|q]_relaxed functions. Signed-off-by: Chanho Park --- arch/riscv/include/asm/io.h | 45 + 1 file changed, 45 insertions(+) diff --git a/arch/riscv/include/asm

[PATCH v3 5/5] configs: visionfive2: Enable JH7110 RNG driver

Enables JH7110 RNG driver to visionfive2 board. Signed-off-by: Chanho Park Reviewed-by: Heinrich Schuchardt --- configs/starfive_visionfive2_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index

[PATCH v3 4/5] riscv: dts: jh7110: Add rng device tree node

Adds jh7110 trng device tree node. Signed-off-by: Chanho Park --- arch/riscv/dts/jh7110.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index ec237a46ffba..13c47f7caa36 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b

[PATCH v3 2/5] clk: starfive: jh7110: Add security clocks

Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG device. Signed-off-by: Chanho Park --- drivers/clk/starfive/clk-jh7110.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 31aaf3340f94

[PATCH v3 0/5] Add support for StarFive JH7110 TRNG driver

rich's R-b tag Chanho Park (5): riscv: import read/write_relaxed functions clk: starfive: jh7110: Add security clocks rng: Add StarFive JH7110 RNG driver riscv: dts: jh7110: Add rng device tree node configs: visionfive2: Enable JH7110 RNG driver arch/riscv/dts/jh7110.dtsi

[PATCH v3 3/5] rng: Add StarFive JH7110 RNG driver

Adds to support JH7110 TRNG driver which is based on linux kernel's jh7110-trng.c. This can support to generate 256-bit random numbers and 128-bit but this makes 256-bit default for convenience. Signed-off-by: Chanho Park --- drivers/rng/Kconfig | 6 + drivers/rng/Makefile

RE: [PATCH v3 3/5] rng: Add StarFive JH7110 RNG driver

Hi, > -Original Message- > From: Heinrich Schuchardt > Sent: Wednesday, November 1, 2023 9:00 PM > To: Chanho Park > Cc: Sughosh Ganu ; u-boot@lists.denx.de; Rick > Chen ; Leo ; Jaehoon Chung > > Subject: Re: [PATCH v3 3/5] rng: Add StarFive JH7110 RNG driv

[PATCH v4 0/5] Add support for StarFive JH7110 TRNG driver

es of probe() which are suggested by Jaehoon Changes from v1: - Patch #3: Apply Heinrich's reviews and his codes - Patch #5: Add Heinrich's R-b tag Chanho Park (5): riscv: import read/write_relaxed functions clk: starfive: jh7110: Add security clocks rng: Add StarFive JH7110 RNG

[PATCH v4 4/5] riscv: dts: jh7110: Add rng device tree node

Adds jh7110 trng device tree node. Signed-off-by: Chanho Park --- arch/riscv/dts/jh7110.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index ec237a46ffba..13c47f7caa36 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b

[PATCH v4 2/5] clk: starfive: jh7110: Add security clocks

Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG device. Signed-off-by: Chanho Park --- drivers/clk/starfive/clk-jh7110.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 31aaf3340f94

[PATCH v4 5/5] configs: visionfive2: Enable JH7110 RNG driver

Enables JH7110 RNG driver to visionfive2 board. Signed-off-by: Chanho Park Reviewed-by: Heinrich Schuchardt --- configs/starfive_visionfive2_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index

[PATCH v4 3/5] rng: Add StarFive JH7110 RNG driver

Adds to support JH7110 TRNG driver which is based on linux kernel's jh7110-trng.c. This can support to generate 256-bit random numbers and 128-bit but this makes 256-bit default for convenience. Signed-off-by: Chanho Park --- drivers/rng/Kconfig | 6 + drivers/rng/Makefile

[PATCH v4 1/5] riscv: import read/write_relaxed functions

This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h to use read/write[b|w|l|q]_relaxed functions. Signed-off-by: Chanho Park --- arch/riscv/include/asm/io.h | 45 + 1 file changed, 45 insertions(+) diff --git a/arch/riscv/include/asm

[PATCH 1/4] clk: starfive: jh7110: Add watchdog clocks

Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110 watchdog device. Signed-off-by: Chanho Park --- drivers/clk/starfive/clk-jh7110.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index

[PATCH 4/4] configs: visionfive2: Enable watchdog driver

Enables StarFive Watchdog driver and WDT command. Signed-off-by: Chanho Park --- configs/starfive_visionfive2_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index b15e7d24db19..7b39a63359dc

[PATCH 2/4] watchdog: Add StarFive Watchdog driver

ave a consistency with the linux driver. Signed-off-by: Chanho Park --- drivers/watchdog/Kconfig| 7 + drivers/watchdog/Makefile | 1 + drivers/watchdog/starfive_wdt.c | 329 3 files changed, 337 insertions(+) create mode 100644 drivers/wat

[PATCH 3/4] riscv: dts: jh7110: Add watchdog device tree node

Adds jh7110 watchdog device tree node. Signed-off-by: Chanho Park --- arch/riscv/dts/jh7110.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 13c47f7caa36..6d2675d6ceac 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b

[PATCH 0/4] Support StarFive Watchdog driver

this patch tries to keep the variant coding style for future work of JH7100 and have a consistency with the Linux driver. Chanho Park (4): clk: starfive: jh7110: Add watchdog clocks watchdog: Add StarFive Watchdog driver riscv: dts: jh7110: Add watchdog device tree node configs: visionfiv

[PATCH 2/3] riscv: timer: add timer_get_boot_us for BOOTSTAGE

timer_get_boot_us function is required to record the boot stages as us-based timestamp. Signed-off-by: Chanho Park --- drivers/timer/riscv_timer.c | 21 + 1 file changed, 21 insertions(+) diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index

[PATCH 1/3] riscv: bootstage: correct bootstage_report guard

age_report(); | ^~~~ | bootstage_error Signed-off-by: Chanho Park --- arch/riscv/lib/bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 276677a5e2f9..cc30efc90498 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch

[PATCH 0/3] bootstage support for risc-v

This adds to support bootstage for risc-v. timer_get_boot_us function is required to record each boot stages with microsecond timestamp. Chanho Park (3): riscv: bootstage: correct bootstage_report guard riscv: timer: add timer_get_boot_us for BOOTSTAGE timer: riscv_aclint_timer: add

[PATCH 3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

timer_get_boot_us function is required to record the boot stages as us-based timestamp. Signed-off-by: Chanho Park --- drivers/timer/riscv_aclint_timer.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/timer/riscv_aclint_timer.c b/drivers/timer

RE: [PATCH] fpga: define dummy fpga_load function for debug build

Hi, > -Original Message- > From: Michal Simek > Sent: Friday, August 25, 2023 4:23 PM > To: Chanho Park ; u-boot@lists.denx.de > Subject: Re: [PATCH] fpga: define dummy fpga_load function for debug build > > Hi, > > On 8/16/23 08:54, Chanho Park wrote: >

[PATCH] spl: bootstage: move bootstage_stash before jumping to image

For IH_OS_OPENSBI and IH_OS_LINUX, there is no chance to stash bootstare record because it will not return after jumping to the image. Hence, this patch moves the location of bootstage_stash before jumping to image. Signed-off-by: Chanho Park --- common/spl/spl.c | 15 --- 1 file

[PATCH v2 1/3] riscv: bootstage: correct bootstage_report guard

age_report(); | ^~~~ | bootstage_error Signed-off-by: Chanho Park --- arch/riscv/lib/bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 276677a5e2f9..cc30efc90498 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch

[PATCH v2 0/3] bootstage support for risc-v

This adds to support bootstage for risc-v. timer_get_boot_us function is required to record each boot stages with microsecond timestamp. Changes from v1: - Correct #ifdef guard for riscv_aclint_timer and riscv_timer Chanho Park (3): riscv: bootstage: correct bootstage_report guard riscv

[PATCH v2 2/3] riscv: timer: add timer_get_boot_us for BOOTSTAGE

timer_get_boot_us function is required to record the boot stages as us-based timestamp. Signed-off-by: Chanho Park --- drivers/timer/riscv_timer.c | 21 + 1 file changed, 21 insertions(+) diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index

[PATCH v2 3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

timer_get_boot_us function is required to record the boot stages as us-based timestamp. Signed-off-by: Chanho Park --- drivers/timer/riscv_aclint_timer.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/timer/riscv_aclint_timer.c b/drivers/timer

RE: [PATCH] fpga: define dummy fpga_load function for debug build

Hi, > -Original Message- > From: Eugen Hristev > Sent: Monday, August 28, 2023 5:47 PM > To: Chanho Park ; 'Michal Simek' > ; u-boot@lists.denx.de > Cc: Simon Glass > Subject: Re: [PATCH] fpga: define dummy fpga_load function for debug build > >

RE: [PATCH RESEND v3] fpga: add inline stub for fpga_load

Hi Eugen, > -Original Message- > From: Eugen Hristev > Sent: Monday, August 28, 2023 8:47 PM > To: Michal Simek ; u-boot@lists.denx.de; > s...@chromium.org; Chanho Park > Subject: Re: [PATCH RESEND v3] fpga: add inline stub for fpga_load > > On 8/28/23 13:53, Mi

[PATCH] spl: add __noreturn attribute to spl_invoke_opensbi function

spl_invoke_opensbi function is not returned to SPL. Thus, we need to set __noreturn function attribute. Signed-off-by: Chanho Park --- common/spl/spl_opensbi.c | 7 --- include/spl.h| 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/common/spl/spl_opensbi.c b

RE: [PATCH] spl: bootstage: move bootstage_stash before jumping to image

Hi Simon, > -Original Message- > From: Simon Glass > Sent: Tuesday, August 29, 2023 2:55 AM > To: Chanho Park > Cc: Nikhil M Jain ; Marek Vasut ; u- > b...@lists.denx.de > Subject: Re: [PATCH] spl: bootstage: move bootstage_stash before jumping > to image > &

[PATCH v2] spl: bootstage: move bootstage_stash before jumping to image

. Signed-off-by: Chanho Park --- Changes from v1 - Separate the final stage bootstage code into spl_bootstage_finish. - As Simon suggests, call the function before jumping to the image. common/spl/spl.c | 24 +--- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a

RE: [PATCH v2] spl: bootstage: move bootstage_stash before jumping to image

Hi Simon, > -Original Message- > From: Simon Glass > Sent: Wednesday, August 30, 2023 1:38 AM > To: Chanho Park > Cc: Nikhil M Jain ; Marek Vasut ; u- > b...@lists.denx.de > Subject: Re: [PATCH v2] spl: bootstage: move bootstage_stash before > jumping to image

RE: [PATCH] fpga: define dummy fpga_load function for debug build

> On 8/16/23 08:54, Chanho Park wrote: > > This fixes below build error when CC_OPTIMIZE_FOR_DEBUG is enabled and > > CONFIG_SPL_FPGA is not enabled. > > I would rewrite this because the connection to SPL_FPGA is just one part > of it. > It is also taken when CONFIG

[PATCH v2] fpga: define dummy fpga_load function for debug build

/spl_fit.c:591: undefined reference to `fpga_load' collect2: error: ld returned 1 exit status Signed-off-by: Chanho Park --- Change from v1: - Rewrite the commit message to include a CONFIG_FPGA include/fpga.h | 8 1 file changed, 8 insertions(+) diff --git a/include/fpga.h b/in

RE: [PATCH v2 2/3] riscv: timer: add timer_get_boot_us for BOOTSTAGE

Hi, > -Original Message- > From: Leo Liang > Sent: Monday, September 4, 2023 4:01 PM > To: Chanho Park > Cc: Rick Chen ; Simon Glass ; u- > b...@lists.denx.de > Subject: Re: [PATCH v2 2/3] riscv: timer: add timer_get_boot_us for > BOOTSTAGE > > Hi Chanho

RE: [PATCH v2 3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

Hi, > -Original Message- > From: Leo Liang > Sent: Monday, September 4, 2023 4:02 PM > To: Chanho Park > Cc: Rick Chen ; Simon Glass ; u- > b...@lists.denx.de > Subject: Re: [PATCH v2 3/3] timer: riscv_aclint_timer: add > timer_get_boot_us for BOOTSTAGE > &g

RE: [PATCH 2/2] risc-v: implement DBCN based debug console

c:30: undefined reference to `sbi_dbcn_write_byte' riscv64-unknown-linux-gnu-ld.bfd: drivers/serial/serial_sbi.o: in function `_debug_uart_init': /data/risc-v/vf2/mainline/u-boot/drivers/serial/serial_sbi.c:24: undefined reference to `sbi_probe_extension' make[2]: *** [/data/risc-v/vf2/mainline/u-boot/scripts/Makefile.spl:527: spl/u-boot-spl] Error 1 Best Regards, Chanho Park

RE: [PATCH v2 0/2] risc-v: implement DBCN based debug console

Hi, > -Original Message- > From: Heinrich Schuchardt > Sent: Monday, September 4, 2023 8:24 PM > To: Rick Chen ; Leo > Cc: Bin Meng ; Anup Patel ; > Chanho Park ; u-boot@lists.denx.de; Heinrich > Schuchardt > Subject: [PATCH v2 0/2] risc-v: implement

RE: [PATCH v2 3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

Hi Simon, > -Original Message- > From: Simon Glass > Sent: Tuesday, September 5, 2023 1:49 AM > To: Chanho Park > Cc: Rick Chen ; Leo ; u- > b...@lists.denx.de > Subject: Re: [PATCH v2 3/3] timer: riscv_aclint_timer: add > timer_get_boot_us for BOOTSTAGE > &

[PATCH v3 0/3] bootstage support for risc-v

This adds to support bootstage for risc-v. timer_get_boot_us function is required to record each boot stages with microsecond timestamp. Changes from v2: - Add a Leo's RB tag of 1/3 patch - Add a description of the calculation formula - Correct the divisor value typo of 3/3 patch Chanho Pa

[PATCH v3 1/3] riscv: bootstage: correct bootstage_report guard

age_report(); | ^~~~ | bootstage_error Signed-off-by: Chanho Park Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/lib/bootm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 276677a5e2f9..cc30efc90498 100644 --- a/arch

[PATCH v3 2/3] riscv: timer: add timer_get_boot_us for BOOTSTAGE

/ 1000) Signed-off-by: Chanho Park --- drivers/timer/riscv_timer.c | 22 ++ 1 file changed, 22 insertions(+) diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c index 28a6a6870b81..169c03dcb5c1 100644 --- a/drivers/timer/riscv_timer.c +++ b/drivers/timer

[PATCH v3 3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

/ 1000) Signed-off-by: Chanho Park --- drivers/timer/riscv_aclint_timer.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/drivers/timer/riscv_aclint_timer.c b/drivers/timer/riscv_aclint_timer.c index e29d527c8d77..73fb87912851 100644 --- a/drivers/timer

RE: [PATCH 1/2] tools: mkimage: Add StarFive SPL image support

Hi, > -Original Message- > From: Heinrich Schuchardt > Sent: Wednesday, September 6, 2023 7:08 PM > To: Rick Chen ; Leo ; Yanhong > Wang > Cc: Simon Glass ; Marc Kleine-Budde ; > Chanho Park ; u-boot@lists.denx.de; Heinrich > Schuchardt > Subject: [PAT

RE: [PATCH 2/2] riscv: dts: starfive: generate u-boot-spl.bin.normal.out

> -Original Message- > From: Heinrich Schuchardt > Sent: Wednesday, September 6, 2023 7:08 PM > To: Rick Chen ; Leo ; Yanhong > Wang > Cc: Simon Glass ; Marc Kleine-Budde ; > Chanho Park ; u-boot@lists.denx.de; Heinrich > Schuchardt > Subject: [PATCH 2/2] ris

RE: [PATCH v3 3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

Hi, > -Original Message- > From: Heinrich Schuchardt > Sent: Thursday, September 7, 2023 2:27 AM > To: Chanho Park ; Simon Glass > > Cc: u-boot@lists.denx.de; Rick Chen ; Leo > > Subject: Re: [PATCH v3 3/3] timer: riscv_aclint_timer: add > timer_get_bo

[PATCH] spl: add __noreturn attribute to spl_invoke_atf function

spl_invoke_atf function will not be returned to SPL. Thus, we need to set __noreturn function attribute to the function. Signed-off-by: Chanho Park --- common/spl/spl_atf.c | 8 include/spl.h| 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/common/spl

[PATCH] configs: visionfive2: enable bootstage configs

Accumulated time: 10,093 dm_f 15,867 dm_r Signed-off-by: Chanho Park --- configs/starfive_visionfive2_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 6590727fe750

[PATCH] dm: core: allow DM_POST_INIT_F notification for TIMER_EARLY

t the arch_cpu_init_dm() even only before relocation") Cc: Simon Glass Cc: Bin Meng Signed-off-by: Chanho Park --- drivers/core/root.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/core/root.c b/drivers/core/root.c index 6775fb0b6575..e939da484b2a 100644 --- a/dr

[PATCH] fpga: define dummy fpga_load function for debug build

This fixes below build error when CC_OPTIMIZE_FOR_DEBUG is enabled and CONFIG_SPL_FPGA is not enabled. ../common/spl/spl_fit.c:591: undefined reference to `fpga_load' collect2: error: ld returned 1 exit status Signed-off-by: Chanho Park --- include/fpga.h | 8 1 file chang

RE: [PATCH] dm: core: allow DM_POST_INIT_F notification for TIMER_EARLY

Hi Simon, > -Original Message- > From: Simon Glass > Sent: Wednesday, August 9, 2023 2:54 AM > To: Chanho Park > Cc: u-boot@lists.denx.de; Bin Meng > Subject: Re: [PATCH] dm: core: allow DM_POST_INIT_F notification for > TIMER_EARLY > > Hi Chanho, >

[PATCH v2 1/2] dm: event: add EVT_DM_POST_INIT_R event type

This patch introduces EVT_DM_POST_INIT_R event type for handling hooks after relocation. Fixes: 55171aedda88 ("dm: Emit the arch_cpu_init_dm() even only before relocation") Suggested-by: Simon Glass Cc: Bin Meng Signed-off-by: Chanho Park --- drivers/core/root.c | 6 -- inclu

[PATCH v2 0/2] introduce EVT_DM_POST_INIT_R to fix VF2 boot fail

sbvj0+...@mail.gmail.com/ Chanho Park (2): dm: event: add EVT_DM_POST_INIT_R event type riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback arch/riscv/cpu/cpu.c | 11 +++ drivers/core/root.c | 6 -- include/event.h | 1 + 3 files changed, 8 insertions(+), 10 dele

[PATCH v2 2/2] riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback

) Thus, we need to move riscv_cpu_probe function in order to register the timer earlier than initr_dm_devices. Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events") Cc: Simon Glass Cc: Bin Meng Signed-off-by: Chanho Park --- arch/riscv/cpu/cpu.c | 11 +++ 1 fi

RE: [PATCH v2 05/21] riscv: Add a reset_cpu() function

> -Original Message- > From: Simon Glass > Sent: Friday, December 15, 2023 1:50 AM > To: U-Boot Mailing List > Cc: Tom Rini ; Simon Glass ; Chanho > Park ; Heinrich Schuchardt ; > Leo ; Nikita Shubin ; Rick Chen > > Subject: [PATCH v2 05/21] riscv: Add a re

RE: [PATCH 09/13] pinctrl: exynos: Add pinctrl support for Exynos850

0.c > new file mode 100644 > index ..2445dd752ea8 > --- /dev/null > +++ b/drivers/pinctrl/exynos/pinctrl-exynos850.c > @@ -0,0 +1,125 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2023 Linaro Ltd. > + * Author: Sam Protsenko > + * > + * Samsung Exynos USI driver (Universal Serial Interface). Typo. It should be a subject for the pinctrl driver. Otherwise, Reviewed-by: Chanho Park

RE: [PATCH 08/13] clk: exynos: Add Exynos850 clock driver

PERI. The UART baud clock is required in the serial driver, to > get its rate for the consequent baud rate calculation. > > Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park

RE: [PATCH 07/13] clk: exynos: Add Samsung clock framework

lk_dm(pll_clk->id, clk); > + } > +} > + > +U_BOOT_DRIVER(samsung_pll0822x_clk) = { > + .name = UBOOT_DM_CLK_SAMSUNG_PLL0822X, > + .id = UCLASS_CLK, > + .ops= &samsung_pll0822x_clk_min_ops, > + .flags = DM_FLAG_PRE_RELOC, > +}; > + > +U_BOOT_DRIVER(samsung_pll0831x_clk) = { > + .name = UBOOT_DM_CLK_SAMSUNG_PLL0831X, > + .id = UCLASS_CLK, > + .ops= &samsung_pll0831x_clk_min_ops, > + .flags = DM_FLAG_PRE_RELOC, > +}; > diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h > new file mode 100644 > index ..3b477369aeb8 > --- /dev/null > +++ b/drivers/clk/exynos/clk-pll.h > @@ -0,0 +1,23 @@ > +/* SPDX-License-Identifier: GPL-2.0+ */ > +/* > + * Copyright (C) 2016 Samsung Electronics > + * Copyright (C) 2023 Linaro Ltd. > + * > + * Authors: > + * Thomas Abraham Ditto. Othewise, Reviewed-by: Chanho Park

RE: [PATCH 05/13] soc: samsung: Add Exynos PMU driver

nction, as the probe function must be always called > for this driver. > > Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park

RE: [PATCH 04/13] soc: samsung: Add Exynos USI driver

d although no > misc operations are implemented, it makes it easier to probe the driver > this way (as compared to UCLASS_NOP) and keep the code compact. > > [1] drivers/soc/samsung/exynos-usi.c > > Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park

RE: [PATCH 06/13] clk: exynos: Move pll code into clk-exynos7420

3] clk: exynos: Move pll code into clk-exynos7420 > > PLL utilities code is only used by clk-exynos7420 driver at the moment. > Move it into clk-exynos7420 to make clk-pll.c file available for CCF PLL > clocks implementation, which is coming in the next patches. > > Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park

[PATCH] watchdog: Correct watchdog timeout print message

000 WDT: Started watchdog@1307 without servicing (60s timeout) After --> StarFive # wdt start 3000 WDT: Started watchdog@1307 without servicing (3s timeout) Fixes: c2fd0ca1a822 ("watchdog: Integrate watchdog triggering into the cyclic framework") Signed-off

RE: [PATCH] watchdog: Correct watchdog timeout print message

> -Original Message- > From: Stefan Roese > Sent: Friday, December 1, 2023 7:39 PM > To: Chanho Park ; u-boot@lists.denx.de > Subject: Re: [PATCH] watchdog: Correct watchdog timeout print message > > On 12/1/23 08:37, Stefan Roese wrote: > > On 11/27/23 02:05,

[PATCH v2] watchdog: Correct watchdog timeout print message

000 WDT: Started watchdog@1307 without servicing (60s timeout) After --> StarFive # wdt start 3000 WDT: Started watchdog@1307 without servicing (3s timeout) Fixes: c2fd0ca1a822 ("watchdog: Integrate watchdog triggering into the cyclic framework") Signed-off-by: Chanho

[PATCH] vexpress64: Fix bootargs when building without NET

‘BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE’ 443 | BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE | ^ Signed-off-by: Chanho Park --- include/configs/vexpress_aemv8.h | 24