Re: [PATCH v2] dt-bindings: riscv: deprecate riscv,isa

mit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. + + zihpm: + type: boolean +description: + The standard Zihpm extension for hardware performance counters, as + ratified in the 20191213 version of the unprivileged ISA + specification. + + ztso: +type: boolean +description: + The standard Ztso extension for total store ordering, as ratified in + commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual. + +additionalProperties: true +... -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html

[[PATCH v2]] riscv: add backtrace support

When debugging, it is useful to have a backtrace to find out what is in the call stack as the previous function (RA) may not have been the culprit. Since this adds size to the build, do not add it by default and avoid putting it in the SPL build if not needed. Signed-off-by: Ben Dooks --- v2

[PATCH 1/2] cache: sifive: clear out the error irqs on init

We are getting a number of cache errors on starting an OS, so to try and avoid this, clear the errors when we first probe the cache. Signed-off-by: Ben Dooks [ben.do...@codethink.co.uk: changed from sifive.com address] --- drivers/cache/cache-sifive-ccache.c | 9 - 1 file changed, 8

[PATCH 2/2] sifive: ccache: add clear LIM area

Add option to clear the LIM area on startup, just in case this is the cause of some of the data-errors on startup. Signed-off-by: Ben Dooks [ben.do...@codethink.co.uk: changed from sifive.com address] --- drivers/cache/Kconfig | 8 ++ drivers/cache/cache-sifive-ccache.c | 40

Re: [PATCH 1/2] cache: sifive: clear out the error irqs on init

On 08/09/2023 14:37, Ben Dooks wrote: We are getting a number of cache errors on starting an OS, so to try and avoid this, clear the errors when we first probe the cache. Signed-off-by: Ben Dooks [ben.do...@codethink.co.uk: changed from sifive.com address] As a follow-up, this hasn't

riscv: asm update for building ubifs

Fix misisng atomic and test_and_{set,clear}_bit macros to allow the ubi/ubifs code to be built for riscv. These are fairly simple but are not being used outside of ubifs on our builds. Ben Dooks (3): riscv: add generic link for riscv: implement local_irq_{save,restore} macros riscv: define

[PATCH 2/3] riscv: implement local_irq_{save,restore} macros

Add implementations of the local_irq_{save,restore} macros so that can be used with riscv. Signed-off-by: Ben Dooks --- arch/riscv/include/asm/system.h | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm

[PATCH 3/3] riscv: define test_and_{set,clear}_bit in asm/bitops.h

These seem to be missing, and trying to build ubifs without them is causing errors due to these being missing. Signed-off-by: Ben Dooks --- arch/riscv/include/asm/bitops.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h

[PATCH 1/3] riscv: add generic link for

Add a link from to the generic one to allow things like ubifs to be built. This can be extended with riscv AMO ops at a later date. Signed-off-by: Ben Dooks --- arch/riscv/include/asm/atomic.h | 14 ++ 1 file changed, 14 insertions(+) create mode 100644 arch/riscv/include/asm

[PATCH] clk: sifive: only build sifive-prci.o for CONFIG_CLK_SIFIVE_PRCI

If we're building non FU540/FU740 SoC drivers, then the sifive-prci.o is not needed. Only build this when CONFIG_CLK_SIFIVE_PRCI is selected. Signed-off-by: Ben Dooks --- drivers/clk/sifive/Makefile | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/clk/s

[PATCH] ubifs: allow loading to above 4GiB

: => ubifsload 0x21 /boot/Image.lzma Loading file '/boot/Image.lzma' to addr 0x... Unhandled exception: Store/AMO access fault Signed-off-by: Ben Dooks --- cmd/ubifs.c | 2 +- fs/ubifs/ubifs.c | 4 ++-- include/ubifs_uboot.h | 2 +- 3 files changed,

[PATCH] riscv: add backtrace support

When debugging, it is useful to have a backtrace to find out what is in the call stack as the previous function (RA) may not have been the culprit. Since this adds size to the build, do not add it by default and avoid putting it in the SPL build if not needed. Signed-off-by: Ben Dooks --- arch

[PATCH] drivers: pci: pcie_dw_common: add upper-limit to iATU

causes the config viewport to become most of memory (obviously stopping the emulated system working correctly) Signed-off-by: Ben Dooks --- drivers/pci/pcie_dw_common.c | 2 ++ drivers/pci/pcie_dw_common.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/pci/pcie_dw_common.c b/drivers

Re: [PATCH] drivers: pci: pcie_dw_common: add upper-limit to iATU

On 20/10/2022 17:13, Bin Meng wrote: Hi Ben, On Thu, Oct 20, 2022 at 11:51 PM Ben Dooks wrote: The 4.6 spec added an upper 32bits to the ATU limit, and since this driver is already assuming the unrolled feature added in the 4.8 specification this really should be set. This is causing a bug

Re: [U-Boot] [PATCH 2/2] board: amlogic: Rename folder for Amlogic boards

gt; > delete mode 100644 board/hardkernel/odroid-c2/odroid-c2.c > > Reviewed-by: Simon Glass > > Although I'm surprised this did not come through as a rename in your patch. > > - Simon > > ___ > linux-amlogic mailing list > linux-

[U-Boot] [PATCH 2/2] SPI: Add S25FL164K flash identifier info

Add the necessary flash entry for the Spansion S25FL164K flash. Tested on Marvell 88F6218 based design. Signed-off-by: Ben Dooks --- drivers/mtd/spi/sf_params.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 462e5c2..c1f243b

[U-Boot] SPI flash ID patches

These are a pair of patches adding some SPI flashes that were evaluated on a Marvell Kirkwood system. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 1/2] SPI: Add S25FL064A and S25FL116K flash information

From: Adnan Ali Add S25FL064A and S25FL116K flash indentifiers. Signed-off-by: Adnan Ali --- drivers/mtd/spi/sf_params.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index 61545ca..462e5c2 100644 --- a/drivers/mtd/spi/sf_params

Re: [U-Boot] [PATCH 1/2] SPI: Add S25FL064A and S25FL116K flash information

On 18/12/14 12:14, Jagan Teki wrote: > On 17 November 2014 at 20:21, Ben Dooks wrote: >> From: Adnan Ali >> >> Add S25FL064A and S25FL116K flash indentifiers. >> >> Signed-off-by: Adnan Ali >> --- >> drivers/mtd/spi/sf_params.c | 2 ++ >>

Re: [U-Boot] [PATCH v3 u-boot 1/3] usb: host: Add simple of glue driver for DWC3 USB Controllers integration

NABLED(CLK) avoidable? [...] Thanks, Neil ___ linux-amlogic mailing list linux-amlo...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic -- Ben Dooks http://www.codethink.c

Re: [U-Boot] [RFC PATCH u-boot] ARM: arch-meson: build memory banks using reported memory from registers

On 2017-10-19 10:04, Neil Armstrong wrote: As discussed at [1], the Amlogic Meson GX SoCs can embed a BL31 firmware and a secondary BL32 firmware. Since mid-2017, the reserved memory address of the BL31 firmware was moved and grown for security reasons. But mainline U-boot and Linux has the o

Re: [U-Boot] [RFC PATCH u-boot v2] ARM: arch-meson: build memory banks using reported memory from registers

On 2017-10-19 14:22, Neil Armstrong wrote: As discussed at [1], the Amlogic Meson GX SoCs can embed a BL31 firmware and a secondary BL32 firmware. Since mid-2017, the reserved memory address of the BL31 firmware was moved and grown for security reasons. But mainline U-boot and Linux has the o

Re: riscv: asm update for building ubifs

On 05/05/2023 09:02, Ben Dooks wrote: Fix misisng atomic and test_and_{set,clear}_bit macros to allow the ubi/ubifs code to be built for riscv. These are fairly simple but are not being used outside of ubifs on our builds. Has anyone had a chance to review these for merging? I may be losing

Re: [PATCH] riscv: add backtrace support

On 15/05/2023 14:03, Ben Dooks wrote: When debugging, it is useful to have a backtrace to find out what is in the call stack as the previous function (RA) may not have been the culprit. Since this adds size to the build, do not add it by default and avoid putting it in the SPL build if not

[PATCHv2] ubifs: allow loading to above 4GiB

: => ubifsload 0x21 /boot/Image.lzma Loading file '/boot/Image.lzma' to addr 0x... Unhandled exception: Store/AMO access fault Signed-off-by: Ben Dooks Signed-off-by: Ben Dooks --- v2: - fixed debug print --- cmd/ubifs.c | 4 ++-- fs/ubifs/ubi

Re: [PATCH] ubifs: allow loading to above 4GiB

On 05/06/2023 08:45, Heiko Schocher wrote: Hello Ben, On 10.05.23 15:41, Ben Dooks wrote: The ubifsload command is truncating any address above 4GiB as it casts this address to an u32, instead of using an unsigned long which most of the other load commands do. Change this to an unsigned long

Re: [PATCH] riscv: add backtrace support

On 14/06/2023 07:25, Bo Gan wrote: On 5/25/23 4:05 AM, Ben Dooks wrote: On 15/05/2023 14:03, Ben Dooks wrote: When debugging, it is useful to have a backtrace to find out what is in the call stack as the previous function (RA) may not have been the culprit. Since this adds size to the build

Re: [PATCH] riscv: add backtrace support

On 15/06/2023 20:01, Bo Gan wrote: On 6/14/23 10:15 AM, Ben Dooks wrote: On 14/06/2023 07:25, Bo Gan wrote: On 5/25/23 4:05 AM, Ben Dooks wrote: On 15/05/2023 14:03, Ben Dooks wrote: When debugging, it is useful to have a backtrace to find out what is in the call stack as the previous

Re: [PATCH 2/3] riscv: implement local_irq_{save,restore} macros

On 2023-06-12 08:47, Leo Liang wrote: Hi Ben, On Fri, May 05, 2023 at 09:02:06AM +0100, Ben Dooks wrote: Add implementations of the local_irq_{save,restore} macros so that can be used with riscv. Signed-off-by: Ben Dooks --- arch/riscv/include/asm/system.h | 15 +++ 1 file

Re: [PATCH 1/1] riscv: CONFIG_SPL_FRAMEPOINTER must depend on CONFIG_SPL

On 11/08/2024 10:51, Heinrich Schuchardt wrote: The CONFIG_SPL_FRAMEPOINTER symbol is only relevant in SPL. Signed-off-by: Heinrich Schuchardt Thanks for spotting Reviewed-by: Ben Dooks --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b

[PATCH] common: add config for board_init() call

ck in the board init file. Signed-off-by: Ben Dooks --- common/Kconfig | 7 +++ common/board_r.c | 3 +-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/common/Kconfig b/common/Kconfig index be517b80eb5..17539079f90 100644 --- a/common/Kconfig +++ b/common/Kconfig @@

Add big-endian build option for riscv

Add the option to allow building a RISC-V system big-endian. This has been tested against our big-endian qemu/cva6 system and is the minimal base to allow a system to run big-endian. We don't yet address IO endian which has been an interesting issue, as some code seems to assume big-endian means

[PATCH v2 2/2] riscv: byteorder: add test for big-endian

Test for big-endian either via __RISCVEB__ which migth be rather old, or check the BYTE_ORDER if the compiler defines it (which should be any modern gcc like v12) Signed-off-by: Ben Dooks --- arch/riscv/include/asm/byteorder.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a

[PATCH v2 1/2] riscv: add build support for big-endian

Add support to build code big-endian if the board supports it. Updates the makefile to pass the correct compiler and elf flags. Signed-off-by: Ben Dooks --- v2: - fixed issue with big v little endian build (+typos) --- arch/riscv/config.mk | 18 ++ 1 file changed, 14 insertions

[PATCH 2/2] riscv: byteorder: add test for big-endian

Test for big-endian either via __RISCVEB__ which migth be rather old, or check the BYTE_ORDER if the compiler defines it (which should be any modern gcc like v12) Signed-off-by: Ben Dooks --- arch/riscv/include/asm/byteorder.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a

riscv: start on work to allow big-endian build

Given we've been doing work on qemu and linux-kernel we started looking at u-boot too. I've done a quick test with our qemu and got a few patches going. It looks like there are only a few updates to get the build working. The only question I have at the moment is with the read/write io macros whic

[PATCH 1/2] riscv: add build support for big-endian

Add support to build code big-endian if the board supports it. Updates the makefile to pass the correct compiler and elf flags. Signed-off-by: Ben Dooks --- arch/riscv/config.mk | 18 ++ 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/riscv/config.mk b/arch

Re: [PATCH 2/2] riscv: byteorder: add test for big-endian

On 10/06/2025 16:33, Tom Rini wrote: On Tue, Jun 10, 2025 at 04:18:50PM +0100, Ben Dooks wrote: Test for big-endian either via __RISCVEB__ which migth be rather old, or check the BYTE_ORDER if the compiler defines it (which should be any modern gcc like v12) Signed-off-by: Ben Dooks