On Tue, Jul 4, 2023 at 5:44 AM Heinrich Schuchardt
wrote:
>
> Describe which numeric values can be used for as scratch options for
> OpenSBI.
>
> Signed-off-by: Heinrich Schuchardt
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> common/spl/Kconfig
ec.adoc
>
> Signed-off-by: Anup Patel
> Signed-off-by: Kautuk Consul
> ---
> arch/riscv/Kconfig | 45
> arch/riscv/include/asm/semihosting.h | 11 ++
> arch/riscv/include/asm/spl.h | 1 +
> arch/riscv/lib/Makefile
On Thu, Sep 14, 2023 at 12:49 PM Heinrich Schuchardt wrote:
>
> On 9/14/23 08:48, Wu, Fei wrote:
> > On 9/14/2023 2:05 PM, Heinrich Schuchardt wrote:
> >>
> >>
> >> Am 14. September 2023 07:30:55 MESZ schrieb Fei Wu :
> >>> In order to enable PCIe passthrough on qemu riscv, the physical memory
> >
Not all RISC-V boards will have memory below 4 GiB.
>
> A weak implementation of dram_init_banksize() exists in common/board_f.c.
>
> See the discussion in
> https://lore.kernel.org/u-boot/545fe813-cb1e-469c-a131-0025c77ae...@canonical.com/T/
>
> Signed-off-by: Heinrich Schucha
s consistency
> > than RVI do in terms of versioning, or no care about backwards
> > compatibility.
> > A boolean property allows us to assign explicit meanings on a per vendor
> > extension basis, backed up by a description of their meanings.
> >
> > fin
> > ===
&g
On Thu, Sep 3, 2020 at 7:32 AM Bin Meng wrote:
>
> Hi Anup,
>
> On Tue, Aug 18, 2020 at 6:03 PM Sean Anderson wrote:
> >
> > On 8/18/20 5:22 AM, Bin Meng wrote:
> > > +Anup Patel
> > >
> > > On Wed, Jul 29, 2020 at 5:57 PM Sean Anderson wrote:
On Thu, Sep 3, 2020 at 8:19 AM Bin Meng wrote:
>
> Hi Anup,
>
> On Thu, Sep 3, 2020 at 10:46 AM Anup Patel wrote:
> >
> > On Thu, Sep 3, 2020 at 7:32 AM Bin Meng wrote:
> > >
> > > Hi Anup,
> > >
> > > On Tue, Aug 18, 2020 at 6:03 PM S
On Thu, Sep 3, 2020 at 4:23 PM Sean Anderson wrote:
>
> On 9/3/20 1:01 AM, Anup Patel wrote:
> > On Thu, Sep 3, 2020 at 8:19 AM Bin Meng wrote:
> >>
> >> Hi Anup,
> >>
> >> On Thu, Sep 3, 2020 at 10:46 AM Anup Patel wrote:
> >&
d kernel memory: 236K
> + [4.282989] This architecture does not have kernel memory
> protection.
> + [4.289390] Run /init as init process
> + Starting syslogd: OK
> + Starting klogd: OK
> + Starting mdev...
> + /etc/init.d/S10mdev: line 9: can't create /proc/sys/kernel/hotplug:
> nonexistent directory
> + [4.354461] mmc0: host does not support reading read-only switch,
> assuming write-enable
> + [4.361778] mmc0: new SDHC card on SPI
> + [4.381184] mmcblk0: mmc0: SC16G 14.8 GiB
> + [4.424975] mmcblk0: p1 p2 p3
> + modprobe: can't change directory to '/lib/modules': No such file or
> directory
> + Initializing random number generator... [5.041362] random: dd:
> uninitialized urandom read (512 bytes read)
> + done.
> + Starting network: [5.240580] macb 1009.ethernet eth0: PHY
> [1009.ethernet-:00] driver [Microsemi VSC8541 SyncE] (irq=POLL)
> + [5.250752] macb 1009.ethernet eth0: configuring for phy/gmii
> link mode
> + udhcpc: started, v1.29.3
> + udhcpc: sending discover
> + [7.301682] macb 1009.ethernet eth0: Link is Up - 100Mbps/Full
> - flow control tx
> + [7.308726] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
> + udhcpc: sending discover
> + udhcpc: sending discover
> + udhcpc: no lease, failing
> + FAIL
> + Starting dropbear sshd: [ 14.309152] random: dropbear:
> uninitialized urandom read (32 bytes read)
> + OK
> +
> + Welcome to Buildroot
> + buildroot login: root
> + Password:
> + #
> --
> 2.17.1
>
Otherwise looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
0:47
> > >To: Pragnesh Patel
> > >Cc: U-Boot Mailing List ; Atish Patra
> > >; Palmer Dabbelt ; Paul
> > >Walmsley ; Jagan Teki
> > >; Troy Benjegerdes
> > >; Anup Patel ; Sagar
> > >Kadam ; Rick Chen
> > >Subject: Re: [PAT
On Fri, Mar 13, 2020 at 2:31 PM Bin Meng wrote:
>
> On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
> wrote:
> >
> > Enable all cache ways from u-boot proper.
>
> U-Boot
>
> >
> > Signed-off-by: Pragnesh Patel
> > ---
> > board/sifive/fu540/Makefile | 1 +
> > board/sifive/fu540/cache.c | 20 +
On Fri, Mar 13, 2020 at 3:52 PM Bin Meng wrote:
>
> Hi Anup,
>
> On Fri, Mar 13, 2020 at 6:02 PM Anup Patel wrote:
> >
> > On Fri, Mar 13, 2020 at 2:31 PM Bin Meng wrote:
> > >
> > > On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
> > > wrote
On Fri, Mar 13, 2020 at 3:52 PM Bin Meng wrote:
>
> Hi Anup,
>
> On Fri, Mar 13, 2020 at 6:02 PM Anup Patel wrote:
> >
> > On Fri, Mar 13, 2020 at 2:31 PM Bin Meng wrote:
> > >
> > > On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel
> > > wrote
On Thu, Oct 31, 2019 at 6:30 AM Alan Kao wrote:
>
> Hi Bin,
>
> Thanks for the critics. Comments below.
> On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote:
> > Hi Rick,
> >
> > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen wrote:
> > >
> > > Hi Bin
> > >
> > > >
> > > > Hi Rick,
> > > >
> >
On Thu, Oct 31, 2019 at 1:42 PM Anup Patel wrote:
>
> On Thu, Oct 31, 2019 at 6:30 AM Alan Kao wrote:
> >
> > Hi Bin,
> >
> > Thanks for the critics. Comments below.
> > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote:
> > > Hi Rick,
>
On Tue, Nov 5, 2019 at 7:19 AM Rick Chen wrote:
>
> Hi Anup
>
> > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel wrote:
> > > >
> > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao wrote:
> > > > >
> > > > > Hi Bin,
> > >
On Wed, Nov 6, 2019 at 12:14 PM Rick Chen wrote:
>
> Hi Anup
>
> >
> > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen wrote:
> > >
> > > Hi Anup
> > >
> > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel
> > > >
On Wed, Nov 6, 2019 at 2:18 PM Anup Patel wrote:
>
> On Wed, Nov 6, 2019 at 12:14 PM Rick Chen wrote:
> >
> > Hi Anup
> >
> > >
> > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen wrote:
> > > >
> > > > Hi Anup
> > > &
On Wed, Nov 6, 2019 at 2:51 PM Rick Chen wrote:
>
> Hi Anup
>
> >
> > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel wrote:
> > >
> > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen wrote:
> > > >
> > > > Hi Anup
> > &g
On Thu, Nov 7, 2019 at 7:04 AM Rick Chen wrote:
>
> Hi Anup
>
> > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen wrote:
> > >
> > > Hi Anup
> > >
> > > >
> > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel wrote:
> > >
On Thu, Nov 7, 2019 at 10:45 AM Anup Patel wrote:
>
> On Thu, Nov 7, 2019 at 7:04 AM Rick Chen wrote:
> >
> > Hi Anup
> >
> > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen wrote:
> > > >
> > > > Hi Anup
> > > >
On Thu, Nov 7, 2019 at 11:40 AM Rick Chen wrote:
>
> Hi Anup
>
> >
> > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel wrote:
> > >
> > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen wrote:
> > > >
> > > > Hi Anup
&g
On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas
wrote:
>
> On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote:
> > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen wrote:
> > > Hi Anup
> > >
> > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel wrote:
> > >
On Thu, Nov 7, 2019 at 5:11 PM Rick Chen wrote:
>
> Hi Anup & Lukas
>
> Anup Patel 於 2019年11月7日 週四 下午6:44寫道：
> >
> > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas
> > wrote:
> > >
> > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote:
>
On Thu, Nov 7, 2019 at 5:14 PM Auer, Lukas
wrote:
>
> On Thu, 2019-11-07 at 16:14 +0530, Anup Patel wrote:
> > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas
> > wrote:
> > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote:
> > > > On Thu, Nov 7, 2019 at
On Fri, Nov 8, 2019 at 6:53 AM Rick Chen wrote:
>
> Hi Anup
>
> >
> > On Thu, Nov 7, 2019 at 5:11 PM Rick Chen wrote:
> > >
> > > Hi Anup & Lukas
> > >
> > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道：
> > > >
> > > &
1-08 at 15:27 +0800, Rick Chen wrote:
> > > > > Hi Atish
> > > > >
> > > > > > Hi Atish
> > > > > >
> > > > > > > On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote:
> > > > > > > > Hi Anup
/riscv/dts/hifive-unleashed-a00.dts | 96 +
> > 3 files changed, 348 insertions(+)
> > create mode 100644 arch/riscv/dts/fu540-c000.dtsi create mode 100644
> > arch/riscv/dts/hifive-unleashed-a00.dts
> >
>
> Reviewed-by: Bin Meng
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
gt; pass dtb during opensbi builds.
> >
> > Signed-off-by: Jagan Teki
> > ---
> > Changes for v4:
> > - Drop abosolete text
> >
> > configs/sifive_fu540_defconfig | 3 ++-
> > doc/board/sifive/fu540.rst | 5 +
> > 2 files changed,
On Fri, Aug 14, 2020 at 11:15 PM Heinrich Schuchardt wrote:
>
> On the Kendryte K210 OpenBSI cannot emulate the rdtime instruction. So we
> have to use the Sifive CLINT driver to provide riscv_get_time() in SMODE.
Can you elaborate why ?
The rdtime instruction should generate an illegal instruct
On Fri, Aug 14, 2020 at 11:35 PM Heinrich Schuchardt wrote:
>
> On 14.08.20 19:52, Anup Patel wrote:
> > On Fri, Aug 14, 2020 at 11:15 PM Heinrich Schuchardt
> > wrote:
> >>
> >> On the Kendryte K210 OpenBSI cannot emulate the rdtime instruction. So we
>
On Sat, Aug 15, 2020 at 12:57 AM Heinrich Schuchardt wrote:
>
> On 8/14/20 8:38 PM, Anup Patel wrote:
> > On Fri, Aug 14, 2020 at 11:35 PM Heinrich Schuchardt
> > wrote:
> >>
> >> On 14.08.20 19:52, Anup Patel wrote:
> >>> On Fri, Aug 14, 20
On Sat, Aug 15, 2020 at 8:37 PM Heinrich Schuchardt wrote:
>
> Am 15. August 2020 16:06:41 MESZ schrieb Anup Patel :
> >On Sat, Aug 15, 2020 at 12:57 AM Heinrich Schuchardt
> > wrote:
> >>
> >> On 8/14/20 8:38 PM, Anup Patel wrote:
> >> > On F
On Sun, Aug 16, 2020 at 3:49 PM Heinrich Schuchardt wrote:
>
> On 8/15/20 5:55 PM, Anup Patel wrote:
> > On Sat, Aug 15, 2020 at 8:37 PM Heinrich Schuchardt
> > wrote:
> >>
> >> Am 15. August 2020 16:06:41 MESZ schrieb Anup Patel :
> >>> On S
On Mon, Jan 20, 2020 at 8:04 PM Pragnesh Patel
wrote:
>
> Hi Anup,
>
> >-Original Message-
> >From: Anup Patel
> >Sent: 20 January 2020 10:26
> >To: Pragnesh Patel
> >Cc: U-Boot Mailing List ; Palmer Dabbelt
> >; Atish Patra
> >Su
On Wed, Jan 22, 2020 at 10:08 AM Anup Patel wrote:
>
> On Mon, Jan 20, 2020 at 8:04 PM Pragnesh Patel
> wrote:
> >
> > Hi Anup,
> >
> > >-----Original Message-
> > >From: Anup Patel
> > >Sent: 20 January 2020 10:26
> > >To
t; +
> +#define DEVICESRESET_DDR_CTRL_RST_N(x)(((x) & 0x1) << 0)
> +#define DEVICESRESET_DDR_AXI_RST_N(x) (((x) & 0x1) << 1)
> +#define DEVICESRESET_DDR_AHB_RST_N(x) (((x) & 0x1) << 2)
> +#define DEVICESRESET_DDR_PHY_RST_N(x) (((x) & 0x1) << 3)
> +#define DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5)
> +
> +#define CLKMUX_STATUS_TLCLKSEL (0x1 << 1)
> +
> +#endif // _SIFIVE_UX00PRCI_H
> diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
> index 2756ed5a77..ef3ae9b650 100644
> --- a/include/configs/sifive-fu540.h
> +++ b/include/configs/sifive-fu540.h
> @@ -11,6 +11,22 @@
>
> #include
>
> +#ifdef CONFIG_SPL
> +
> +#define CONFIG_SPL_MAX_SIZE0x0010
> +#define CONFIG_SPL_BSS_START_ADDR 0x8500
> +#define CONFIG_SPL_BSS_MAX_SIZE0x0010
> +#define CONFIG_SYS_SPL_MALLOC_START(CONFIG_SPL_BSS_START_ADDR + \
> +CONFIG_SPL_BSS_MAX_SIZE)
> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0010
> +
> +#define CONFIG_SPL_LOAD_FIT_ADDRESS0x8400
> +
> +#define CONFIG_SPL_STACK (0x0800 + 0x001D - \
> +GENERATED_GBL_DATA_SIZE)
> +
> +#endif
> +
> #define CONFIG_SYS_SDRAM_BASE 0x8000
> #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_SDRAM_BASE +
> SZ_2M)
>
> @@ -24,6 +40,7 @@
>
> /* Environment options */
>
> +#ifndef CONFIG_SPL_BUILD
> #define BOOT_TARGET_DEVICES(func) \
> func(MMC, mmc, 0) \
> func(DHCP, dhcp, na)
> @@ -43,5 +60,6 @@
> #define CONFIG_PREBOOT \
> "setenv fdt_addr ${fdtcontroladdr};" \
> "fdt addr ${fdtcontroladdr};"
> +#endif
>
> #endif /* __CONFIG_H */
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
540.c
> index b81003aa6f..7fde881e72 100644
> --- a/board/sifive/fu540/fu540.c
> +++ b/board/sifive/fu540/fu540.c
> @@ -13,6 +13,8 @@
> #include
> #include
>
> +#include "cache.h"
> +
> /*
> * This define is a value used for error/unknown serial.
> * If we
diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS
> index 702d803ad8..909a1bf300 100644
> --- a/board/sifive/fu540/MAINTAINERS
> +++ b/board/sifive/fu540/MAINTAINERS
> @@ -1,9 +1,10 @@
> SiFive FU540 BOARD
> M: Paul Walmsley
> -M: Palmer Dabbelt
On Fri, Jan 24, 2020 at 12:21 PM Jagan Teki wrote:
>
> On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
> wrote:
> >
> > With sifive_fu540_spl_defconfig:
> >
> > U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
> > u-boot-spl.bin) and runs in L2 LIM in machine mode and then lo
On Fri, Jan 24, 2020 at 5:49 PM Pragnesh Patel
wrote:
>
> Add ddr4 controller and phy related files
>
> Signed-off-by: Pragnesh Patel
> ---
> board/sifive/fu540/Makefile|4 +
> board/sifive/fu540/ddr.c | 868
> board/sifive/fu540/regconfig-ctl.h | 270
almsley ( Sifive)
> >; Troy Benjegerdes ( Sifive)
> >; Anup Patel ; Sagar
> >Kadam
> >Subject: Re: [PATCH v3 07/10] configs: fu540: Add config file for U-boot SPL
> >
> >On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
> >wrote:
> >>
> >>
On Mon, Jan 27, 2020 at 1:19 PM Pragnesh Patel
wrote:
>
>
> >-Original Message-----
> >From: Anup Patel
> >Sent: 25 January 2020 14:12
> >To: Jagan Teki
> >Cc: Pragnesh Patel ; Atish Patra
> >; Palmer Dabbelt ; U-
> >Boot-Denx
> >Su
On Tue, Dec 31, 2019 at 7:29 PM Pragnesh Patel
wrote:
>
> This series add support for SPL to FU540. This series depends on
> https://patchwork.ozlabs.org/patch/1196703/
> (riscv: dts: Add hifive-unleashed-a00 dts from Linux)
>
> U-Boot SPL can boot from L2 LIM (0x0800_) and jump to
> OpenSBI(F
On Fri, Jan 17, 2020 at 6:16 PM Pragnesh Patel
wrote:
>
> This series add support for SPL to FU540. This series depends on
> https://patchwork.ozlabs.org/patch/1196703/
> (riscv: dts: Add hifive-unleashed-a00 dts from Linux)
>
> U-Boot SPL can boot from L2 LIM (0x0800_) and jump to
> OpenSBI(F
On Fri, Jan 17, 2020 at 6:18 PM Pragnesh Patel
wrote:
>
> Add descriptions about U-Boot SPL feature and how to build and run.
>
> Signed-off-by: Pragnesh Patel
> ---
> doc/board/sifive/fu540.rst | 370 +
> 1 file changed, 370 insertions(+)
>
> diff --git a/doc
iowrite32(((write_data >> bit) & 1),
> + ®s->pdin);
> + mdelay(1);
> +
> + iowrite32(0x01, ®s->pwe);
> + mdelay(1);
> + iowrite32(0x00, ®s->pwe);
> + mdelay(1);
> + }
> + }
> +
> + iowrite32(0x00, ®s->pas);
> + }
> +
> + // shut down
> + iowrite32(0x00, ®s->pwe);
> + iowrite32(0x00, ®s->pprog);
> + iowrite32(0x00, ®s->pce);
> + iowrite32(0x00, ®s->ptm);
> +
> + iowrite32(0x00, ®s->ptrim);
> + iowrite32(0x00, ®s->pdstb);
> +
> + return 0;
> +}
> +
> +static int hifive_otp_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct hifive_otp_platdata *plat = dev_get_platdata(dev);
> +
> + plat->regs = dev_read_addr_ptr(dev);
> + return 0;
> +}
> +
> +static const struct misc_ops hifive_otp_ops = {
> + .read = hifive_otp_read,
> + .write = hifive_otp_write,
> +};
> +
> +static const struct udevice_id hifive_otp_ids[] = {
> + { .compatible = "sifive,fu540-otp" },
> + {}
> +};
> +
> +U_BOOT_DRIVER(hifive_otp) = {
> + .name = "hifive_otp",
> + .id = UCLASS_MISC,
> + .of_match = hifive_otp_ids,
> + .ofdata_to_platdata = hifive_otp_ofdata_to_platdata,
> + .platdata_auto_alloc_size = sizeof(struct hifive_otp_platdata),
> + .ops = &hifive_otp_ops,
> +};
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
@@ -12,6 +12,9 @@ config SYS_CPU
> config SYS_CONFIG_NAME
> default "sifive-fu540"
>
> +config SYS_SOC
> + default "fu540"
> +
> config SYS_TEXT_BASE
> default 0x8000 if !RISCV_SMODE
> default 0x8020 if RISCV_SMODE
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
On Fri, Jan 17, 2020 at 6:17 PM Pragnesh Patel
wrote:
>
> Add fu540 SoC specific header files
>
> Signed-off-by: Pragnesh Patel
> ---
> arch/riscv/include/asm/arch-fu540/cache.h | 42 ++
> arch/riscv/include/asm/arch-fu540/gpio.h | 14
> arch/riscv/include/asm/arch-fu540/otp.h
>
> .bss : {
> __bss_start = .;
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
crc16.o
> +obj-$(CONFIG_MMC_SPI) += crc7.o
> obj-$(CONFIG_$(SPL_TPL_)HASH_SUPPORT) += crc16.o
> obj-y += net_utils.o
> endif
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
i
> b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> index bec0d19134..9b59f4ee14 100644
> --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
> @@ -4,3 +4,21 @@
> */
>
> #include "fu540-c000-u-boot.dtsi"
> +
> +/ {
> + hfclk {
> + u-boot,dm-spl;
> + };
> +
> + rtcclk {
> + u-boot,dm-spl;
> + };
> +};
> +
> +&qspi2 {
> +
> + mmc@0 {
> + u-boot,dm-spl;
> + };
> +
> +};
> --
> 2.17.1
>
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
On Fri, Jan 17, 2020 at 6:18 PM Pragnesh Patel
wrote:
>
> Add header files needed for U-boot SPL
>
> Signed-off-by: Pragnesh Patel
First of all, PATCH7 and PATCH8 does not make sense.
Instead of PATCH7 and PATCH8, we should have following
patch breakup:
1. A PATCH for adding ddrregs.c,required
On Fri, Jan 17, 2020 at 6:18 PM Pragnesh Patel
wrote:
>
> This patch provides sifive_fu540_spl_defconfig which can support
> U-boot SPL to boot from L2 LIM (0x0800_) and then boot U-boot
> FIT image including OpenSBI FW_DYNAMIC firmware and U-Boot proper
> images from MMC boot devices.
>
> Wit
BOOT_PRINTS.
>
> Link:
> https://github.com/riscv-software-src/opensbi/blob/master/docs/firmware/fw_dynamic.md
> Signed-off-by: Nikita Shubin
Looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> common/spl/Kconfig | 8
> common/spl/spl_opensbi.c |
then the board config can set the CONFIG_DMA_ADDR_T_64BIT.
Please see above suggestion.
Regards,
Anup
>
> Regards
> Padmarao
>
> On Sun, Nov 15, 2020 at 5:40 PM Anup Patel wrote:
>>
>> On Tue, Nov 10, 2020 at 4:16 PM Padmarao Begari
>> wrote:
>> >
>> >
Hi Michael,
Set bootargs to "root=/dev/vda2 rootwait console=ttyS0 earlycon=sbi" in
U-Boot before doing bootm
Regards,
Anup
On Wed, 2 Dec, 2020, 12:51 Michael Opdenacker, <
michael.opdenac...@bootlin.com> wrote:
> Greetings,
>
> To prepare an embedded Linux demo (on RiscV), I'm trying to boot L
On 22 November 2013 07:24, Christoffer Dall wrote:
> On 21 November 2013 07:04, Marc Zyngier wrote:
>> Hi Rob,
>>
>> On 21/11/13 14:28, Rob Herring wrote:
>>> On Thu, Nov 21, 2013 at 2:59 AM, Marc Zyngier wrote:
PSCI is an ARM standard that provides a generic interface that
supervisory
On Fri, Nov 22, 2013 at 2:10 PM, Ian Campbell wrote:
> On Thu, 2013-11-21 at 15:04 +, Marc Zyngier wrote:
>> Hi Rob,
>>
>> On 21/11/13 14:28, Rob Herring wrote:
>> > On Thu, Nov 21, 2013 at 2:59 AM, Marc Zyngier wrote:
>> >> PSCI is an ARM standard that provides a generic interface that
>> >>
On Fri, Nov 22, 2013 at 2:12 PM, Ian Campbell wrote:
> On Fri, 2013-11-22 at 09:28 +0530, Anup Patel wrote:
>> An Independent binary of a secured firmware makes more sense here.
>> Also, if secured firmware is an independent binary then it need not be
>> open source.
>
&
Hi All,
Is it possible to include this series for next U-Boot release?
Regards,
Anup
___
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U-Boot@lists.denx.de
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On Mon, Nov 26, 2018 at 2:06 PM Rick Chen wrote:
>
> > Hi All,
> >
> >
> >
> > Is it possible to include this series for next U-Boot release?
>
> Hi Anup
>
> Yes.
>
> I will do some verification.
> And prepare the PR ASAP.
>
> Can you prepare a version which will be rebase on the latest u-boot-ris
" from RISCV_SMODE kconfig option
- Replaced '-smode_' in defconfig names with '_smode_'
Changes since v1:
- Rebased upon latest git://git.denx.de/u-boot-riscv.git
- Add details in cover letter for running u-boot in S-mode
using BBL
Anup Patel (4):
riscv: A
mhartid CSR read.
In-future, we will have more patches to avoid accessing misa and
mhartid CSRs from S-mode.
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Lukas Auer
---
arch/riscv/Kconfig| 5 +
arch/riscv/cpu/start.S| 33
This patch adds S-mode defconfigs for QEMU virt machine so
that we can run u-boot in S-mode on QEMU using M-mode runtime
firmware (BBL or equivalent).
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Lukas Auer
---
board/emulation/qemu-riscv/MAINTAINERS | 2
/reserves memory range
0x8000 to 0x8020 because it runs in S-mode.
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Lukas Auer
---
board/emulation/qemu-riscv/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/emulation/qemu
Currently, the RISC-V U-Boot is saving a2 register at
CONFIG_SYS_DRAM_BASE in start.S which does not make sense
because there is no information passed by previous booting
stage in a2 register.
This patch removes redundant a2 store on DRAM base.
Signed-off-by: Anup Patel
---
arch/riscv/cpu
previous booting stage in a2
> > > > > register.
> > > > >
> > > > > This patch removes redundant a2 store on DRAM base.
> > > > >
> > > > > Signed-off-by: Anup Patel
> > > > > ---
> > > > > arch/
On Tue, Nov 27, 2018 at 10:50 AM Rick Chen wrote:
>
> Anup Patel 於 2018年11月27日 週二 上午11:28寫道：
> >
> > On Tue, Nov 27, 2018 at 8:50 AM Rick Chen wrote:
> > >
> > > > > > > Currently, the RISC-V U-Boot is saving a2 register at
> > > > >
On Tue, Nov 27, 2018 at 11:14 AM Anup Patel wrote:
>
> On Tue, Nov 27, 2018 at 10:50 AM Rick Chen wrote:
> >
> > Anup Patel 於 2018年11月27日 週二 上午11:28寫道：
> > >
> > > On Tue, Nov 27, 2018 at 8:50 AM Rick Chen wrote:
> > > >
> > > > &
On Tue, 27 Nov, 2018, 11:38 AM Rick Chen Anup Patel 於 2018年11月27日 週二 下午1:47寫道：
> >
> > On Tue, Nov 27, 2018 at 11:14 AM Anup Patel wrote:
> > >
> > > On Tue, Nov 27, 2018 at 10:50 AM Rick Chen
> wrote:
> > > >
> > > > Anup Patel 於 201
On Tue, Nov 27, 2018 at 12:00 PM Rick Chen wrote:
>
> Anup Patel 於 2018年11月27日 週二 下午2:14寫道：
> >
> >
> >
> > On Tue, 27 Nov, 2018, 11:38 AM Rick Chen >>
> >> Anup Patel 於 2018年11月27日 週二 下午1:47寫道：
> >> >
> >> > On Tue, Nov 27,
SR read.
> > >
> > > In-future, we will have more patches to avoid accessing misa and mhartid
> > > CSRs
> > > from S-mode.
> > >
> > > Signed-off-by: Anup Patel
> > > Reviewed-by: Bin Meng
> > > Tested-by: Bin Meng
> > >
On Tue, Nov 27, 2018 at 12:14 PM Rick Chen wrote:
>
> > > > > > When we run U-Boot in S-mode the BBL runs from 0x8000 so this
> > > > > > two lines corrupts BBL instructions.
>
> Hi Anup
>
> You said
> Your patchset based upon git://git.denx.de/u-boot-riscv.git
>
> Why you announce this proble
On Tue, Nov 27, 2018 at 12:30 PM Rick Chen wrote:
>
> Anup Patel 於 2018年11月27日 週二 下午2:40寫道：
> >
> > On Tue, Nov 27, 2018 at 12:00 PM Rick Chen wrote:
> > >
> > > Anup Patel 於 2018年11月27日 週二 下午2:14寫道：
> > > >
> > > >
> > > >
On Tue, Nov 27, 2018 at 1:26 PM Anup Patel wrote:
>
> On Tue, Nov 27, 2018 at 12:30 PM Rick Chen wrote:
> >
> > Anup Patel 於 2018年11月27日 週二 下午2:40寫道：
> > >
> > > On Tue, Nov 27, 2018 at 12:00 PM Rick Chen wrote:
> > > &g
On Tue, Nov 27, 2018 at 4:17 PM Alexander Graf wrote:
>
>
>
> On 27.11.18 07:52, Anup Patel wrote:
> > On Tue, Nov 27, 2018 at 12:09 PM Rick Chen wrote:
> >>
> >>>> Subject: [PATCH v5 1/4] riscv: Add kconfig option to run U-Boot in S-mode
> >>&
On Mon, Nov 26, 2018 at 4:13 PM Anup Patel wrote:
>
> This patchset allows us runing u-boot in S-mode which is
> useful on platforms where M-mode runtime firmware is an
> independent firmware and u-boot is used as last stage OS
> bootloader.
>
> The patchset based upon git
On Fri, Nov 30, 2018 at 12:34 PM Rick Chen wrote:
>
> Anup Patel 於 2018年11月27日 週二 下午8:38寫道：
> >
> > On Tue, Nov 27, 2018 at 4:17 PM Alexander Graf wrote:
> > >
> > >
> > >
> > > On 27.11.18 07:52, Anup Patel wrote:
>
with '_smode_'
Changes since v1:
- Rebased upon latest git://git.denx.de/u-boot-riscv.git
- Add details in cover letter for running u-boot in S-mode
using BBL
Anup Patel (3):
riscv: Add kconfig option to run U-Boot in S-mode
riscv: qemu: Use different SYS_TEXT_BASE for S-mode
r
mhartid CSR read.
In-future, we will have more patches to avoid accessing misa and
mhartid CSRs from S-mode.
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Lukas Auer
---
arch/riscv/Kconfig| 5 +
arch/riscv/cpu/start.S| 23
This patch adds S-mode defconfigs for QEMU virt machine so
that we can run u-boot in S-mode on QEMU using M-mode runtime
firmware (BBL or equivalent).
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Lukas Auer
---
board/emulation/qemu-riscv/MAINTAINERS | 2
/reserves memory range
0x8000 to 0x8020 because it runs in S-mode.
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Lukas Auer
---
board/emulation/qemu-riscv/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/emulation/qemu
kconfig option
- Replaced '-smode_' in defconfig names with '_smode_'
Changes since v1:
- Rebased upon latest git://git.denx.de/u-boot-riscv.git
- Add details in cover letter for running u-boot in S-mode
using BBL
Anup Patel (4):
riscv: Add kconfig option to run U-Boot i
mhartid CSR read.
In-future, we will have more patches to avoid accessing misa and
mhartid CSRs from S-mode.
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Lukas Auer
---
arch/riscv/Kconfig| 5 +
arch/riscv/cpu/start.S| 23
/reserves memory range
0x8000 to 0x8020 because it runs in S-mode.
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Lukas Auer
---
board/emulation/qemu-riscv/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/emulation/qemu
This patch adds S-mode defconfigs for QEMU virt machine so
that we can run u-boot in S-mode on QEMU using M-mode runtime
firmware (BBL or equivalent).
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
Reviewed-by: Lukas Auer
---
board/emulation/qemu-riscv/MAINTAINERS | 2
mentation for U-Boot
running in S-mode. For U-Boot running in M-mode, specific timer
drivers will have to be provided.
Signed-off-by: Anup Patel
---
arch/Kconfig| 1 -
arch/riscv/Kconfig | 22 +++
arch/riscv/lib/Makefile | 1 +
arch/ris
On Mon, Dec 3, 2018 at 12:06 PM Bin Meng wrote:
>
> Hi Anup,
>
> On Mon, Dec 3, 2018 at 1:28 PM Anup Patel wrote:
> >
> > When running in S-mode, we can use rdtime and rdtimeh instructions
> > for reading timer ticks (just like Linux). The frequency of timer
> &
On Mon, Dec 3, 2018 at 12:32 PM Bin Meng wrote:
>
> Hi Anup,
>
> On Mon, Dec 3, 2018 at 2:43 PM Anup Patel wrote:
> >
> > On Mon, Dec 3, 2018 at 12:06 PM Bin Meng wrote:
> > >
> > > Hi Anup,
> > >
> > > On Mon, Dec 3, 2018 at 1:28 PM A
On Mon, Dec 3, 2018 at 12:56 PM Bin Meng wrote:
>
> Hi Anup,
>
> On Mon, Dec 3, 2018 at 3:19 PM Anup Patel wrote:
> >
> > On Mon, Dec 3, 2018 at 12:32 PM Bin Meng wrote:
> > >
> > > Hi Anup,
> > >
> > > On Mon, Dec 3, 2018 at 2:43 PM
On Mon, Dec 3, 2018 at 1:08 PM Bin Meng wrote:
>
> Hi Anup,
>
> On Mon, Dec 3, 2018 at 3:31 PM Anup Patel wrote:
> >
> > On Mon, Dec 3, 2018 at 12:56 PM Bin Meng wrote:
> > >
> > > Hi Anup,
> > >
> > > On Mon, Dec 3, 2018 at 3:19 PM
On Tue, Nov 13, 2018 at 1:47 PM Bin Meng wrote:
>
> This adds DM drivers to support RISC-V CPU and timer.
>
> The U-Boot RISC-V SBI support is still working in progress.
> Some patches in this series like adding CSR numbers, exception
> numbers, are prerequisites for the SBI implementation, but it
On Mon, Dec 3, 2018 at 1:27 PM Bin Meng wrote:
>
> Hi Anup,
>
> On Mon, Dec 3, 2018 at 3:44 PM Anup Patel wrote:
> >
> > On Mon, Dec 3, 2018 at 1:08 PM Bin Meng wrote:
> > >
> > > Hi Anup,
> > >
> > > On Mon, Dec 3, 2018 at 3:31 PM Anu
On Mon, Dec 3, 2018 at 2:16 PM Bin Meng wrote:
>
> Hi Anup,
>
> On Mon, Dec 3, 2018 at 4:12 PM Anup Patel wrote:
> >
> > On Mon, Dec 3, 2018 at 1:27 PM Bin Meng wrote:
> > >
> > > Hi Anup,
> > >
> > > On Mon, Dec 3, 2018 at 3:44 PM An
On Tue, Dec 4, 2018 at 1:44 PM Bin Meng wrote:
>
> Hi Rick,
>
> On Tue, Dec 4, 2018 at 3:12 PM Rick Chen wrote:
> >
> > > > From: Anup Patel [mailto:a...@brainfault.org]
> > > > Sent: Monday, December 03, 2018 6:30 PM
> > > > To: Bi
This patch adds SiFive UART driver. The driver is 100% DM driver
and it determines input clock using clk framework.
Signed-off-by: Anup Patel
---
drivers/serial/Kconfig | 13 +++
drivers/serial/Makefile| 1 +
drivers/serial/serial_sifive.c | 193
UBoot tree
(git://git.denx.de/u-boot-riscv.git) at commit id
ce41c65382300b4be2b84df3c06c2aa6c591741d
Anup Patel (2):
drivers: serial: Add SiFive UART driver
riscv: qemu: Enable SiFive UART driver in defconfigs
configs/qemu-riscv32_defconfig | 1 +
configs/qemu-riscv32_smode_defconfig
This patch enables SiFive UART driver in all QEMU RISC-V defconfigs.
Signed-off-by: Anup Patel
---
configs/qemu-riscv32_defconfig | 1 +
configs/qemu-riscv32_smode_defconfig | 1 +
configs/qemu-riscv64_defconfig | 1 +
configs/qemu-riscv64_smode_defconfig | 1 +
4 files changed, 4
Hi Bin,
On Tue, Nov 13, 2018 at 1:47 PM Bin Meng wrote:
>
> This adds DM drivers to support RISC-V CPU and timer.
>
> The U-Boot RISC-V SBI support is still working in progress.
> Some patches in this series like adding CSR numbers, exception
> numbers, are prerequisites for the SBI implementatio
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