On 15.06.22 21:42, Rafał Miłecki wrote:
> From: Rafał Miłecki
>
> MTD subsystem API allows interacting with MTD devices (e.g. reading,
> writing, handling bad blocks). So far a random driver could get MTD
> device only by its name (get_mtd_device_nm()). This change allows
> getting them also by a
Hi,
On 6/16/22 18:37, Patrick Delaunay wrote:
The third parameter of dfu_alt_add(), the string description of alternate,
is build in stm32prog_alt_add() with a unnecessary character ';' at the
end of the string.
This separator was required in the first implementation of
dfu_alt_add() but is no
Hi
On 6/13/22 11:55, Marek Vasut wrote:
Add another mux option for UART3 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut
Cc: Patrice Chotard
Cc: Patrick Delaunay
---
arch/arm/dts/stm32mp15-pinctrl.dtsi | 41 +
1 file changed, 41 insertions(+
Hi,
On 6/13/22 11:55, Marek Vasut wrote:
Add another mux option for UART4 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut
Cc: Patrice Chotard
Cc: Patrick Delaunay
---
arch/arm/dts/stm32mp15-pinctrl.dtsi | 30 +
1 file changed, 30 insertions(
Hi,
On 6/13/22 11:55, Marek Vasut wrote:
Add another mux option for UART5 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut
Cc: Patrice Chotard
Cc: Patrick Delaunay
---
arch/arm/dts/stm32mp15-pinctrl.dtsi | 13 +
1 file changed, 13 insertions(+)
Applied
Hi,
On 6/13/22 11:55, Marek Vasut wrote:
Add another mux option for CAN1 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut
Cc: Patrice Chotard
Cc: Patrick Delaunay
---
arch/arm/dts/stm32mp15-pinctrl.dtsi | 20
1 file changed, 20 insertions(+)
Ap
Hi,
On 6/13/22 11:55, Marek Vasut wrote:
Add another mux option for SPI2 pins, this is used on DRC Compact board.
Signed-off-by: Marek Vasut
Cc: Patrice Chotard
Cc: Patrick Delaunay
---
arch/arm/dts/stm32mp15-pinctrl.dtsi | 15 +++
1 file changed, 15 insertions(+)
Applied
Hi,
On 6/13/22 11:55, Marek Vasut wrote:
Add DT for DH DRC Compact unit, which is a universal controller device.
The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD
card slot, eMMC and SDIO Wi-Fi.
Signed-off-by: Marek Vasut
Cc: Patrice Chotard
Cc: Patrick Delaunay
---
arc
On Fri, 17 Jun 2022 at 06:38, Takahiro Akashi
wrote:
>
> Sughosh,
>
> On Wed, Jun 15, 2022 at 05:40:12PM +0530, Sughosh Ganu wrote:
> > On Wed, 15 Jun 2022 at 11:07, Takahiro Akashi
> > wrote:
> > >
> > > On Thu, Jun 09, 2022 at 06:00:10PM +0530, Sughosh Ganu wrote:
> > > > Add a python test scri
Takahiro,
On Fri, 17 Jun 2022 at 06:16, Takahiro Akashi
wrote:
>
> Sughosh,
>
> On Thu, Jun 16, 2022 at 12:42:08PM +0530, Sughosh Ganu wrote:
> > hi Takahiro,
> >
> > On Thu, 16 Jun 2022 at 06:31, Takahiro Akashi
> > wrote:
> > >
> > > Sughosh,
> > >
> > > On Wed, Jun 15, 2022 at 04:19:56PM +053
Hi,
On 5/6/22 16:06, Patrick Delaunay wrote:
Add initial support of STM32MP13 family based on v5.18-rc2
Signed-off-by: Patrick Delaunay
---
arch/arm/dts/stm32mp13-pinctrl.dtsi | 123 ++
arch/arm/dts/stm32mp131.dtsi| 358
arch/arm/dts/stm32mp133
Hi,
On 5/6/22 16:06, Patrick Delaunay wrote:
The SPL is only supported by STM32MP15x not by all the
SOC with STM32MP arch.
Only TFABOOT is supported in next products.
Signed-off-by: Patrick Delaunay
Signed-off-by: Patrick Delaunay
---
arch/arm/Kconfig | 1 -
arch/arm/mach-stm
Hi,
On 5/6/22 16:06, Patrick Delaunay wrote:
As the get_otp() helper function in bsec are common for all STM32MP family,
move this function in bsec driver
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/bsec.c | 17 +
arch/arm/mach-stm32mp/cpu.c
Hi,
On 5/6/22 16:06, Patrick Delaunay wrote:
Move code and defines only needed for CONFIG_STM32MP15x in stm32mp15x.c
when low level init without TFABOOT is supported.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/Makefile| 2 +
arch/arm/mach-stm32mp/cpu.c
Hi,
On 5/6/22 16:06, Patrick Delaunay wrote:
Add mandatory choice for SOC support in ARCH_STM32MP.
This patch is a preliminary step for new SOC introduction
in STM32MP family.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/Kconfig | 23 +--
configs/stm
Hi,
On 5/6/22 16:06, Patrick Delaunay wrote:
Add sub Kconfig for each SOC in the STM32 CPU family.
It is a preliminary step to introduce a new SOC in the STM32MP family.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/Kconfig | 119 +---
arch/arm/ma
Hi,
On 5/6/22 16:06, Patrick Delaunay wrote:
Add config CONFIG_STM32MP15_PWR to handle the
access on regulators managed by the PWR driver defined in
pwr_regulator.c
This driver is only used in U-Boot by STM32MP15x family.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/Kconfig.15
Hi,
Some ad
On 5/6/22 16:06, Patrick Delaunay wrote:
Introduce the code in mach-stm32mp and the configuration file
stm32mp13_defconfig for the new STM32MP family.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/Kconfig | 21 +++-
arch/arm/mach-stm32mp/Kconfig.13
Hi,
On 5/6/22 16:06, Patrick Delaunay wrote:
Add support of several MAC address in OTP (3 32bits OTP word for
2 MAC address) for SOCs in STM32MP13x family: STM32MP133 and STM32MP135.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/cpu.c | 41 ---
Hi,
On 5/6/22 16:06, Patrick Delaunay wrote:
Add support for "st,stm32mp135-pinctrl" for STM32MP13x
Signed-off-by: Patrick Delaunay
---
drivers/pinctrl/pinctrl_stm32.c | 1 +
1 file changed, 1 insertion(+)
Applied to u-boot-stm/next, thanks!
Regards
Patrick
Hi,
Accepted with minor modification.
On 5/6/22 16:06, Patrick Delaunay wrote:
Add stm32mp15x prefix to all STM32MP15x board specific function,
this patch is a preliminary step for STM32MP13x support.
This patch also add the RCC probe to avoid circular access with
usbphyc probe as clk provide
Hi,
On 5/6/22 16:06, Patrick Delaunay wrote:
Add support for new compatible "st,stm32mp13-ddr" to manage the
DDR sub system (Controller and PHY) in STM32MP13x SOC:
- only one AXI port
- support of 16 port output (MEMC_DRAM_DATA_WIDTH = 2)
The STM32MP15x SOC have 2 AXI ports and 32 bits support.
Hi,
On 5/6/22 16:06, Patrick Delaunay wrote:
Although not recommended, the reset property could be made optional.
This way the driver will probe even if no reset property is provided
in an sdmmc node in DT. This reset is already optional in Linux.
Signed-off-by: Yann Gautier
Signed-off-by: Pat
Hi Tom,
Please pull the SoCFPGA changes as shown in below.
Thanks.
Best regards,
Tien Fong
The following changes since commit c18e5fb055ab789f58434e3cb432582adee0134c:
dtoc: Update test_src_scan.py for new tegra compatibles (2022-06-14 13:59:23
-0400)
are available in the Git repository a
Hi,
On 5/6/22 16:06, Patrick Delaunay wrote:
Compile the device tree of STM32MP13x boards and add the needed
U-Boot add-on.
Signed-off-by: Patrick Delaunay
---
arch/arm/dts/Makefile | 3 +
arch/arm/dts/stm32mp13-u-boot.dtsi | 91 +
arch/arm/
Hi
some adaptation for Kconfig migration in next branch
On 5/6/22 16:06, Patrick Delaunay wrote:
Add a initial config for STM32M13x SOC family, using the stm32mp135f-dk
device tree.
Signed-off-by: Patrick Delaunay
---
board/st/stm32mp1/MAINTAINERS | 1 +
configs/stm32mp13_defconfig | 5
Hi,
On 5/6/22 16:06, Patrick Delaunay wrote:
Add in U-Boot documentation the quick instruction for
setup the STMicroelectronics STM32MP13x boards.
Signed-off-by: Patrick Delaunay
---
doc/board/st/stm32mp1.rst | 181 ++
1 file changed, 125 insertions(+),
Hi,
On 5/9/22 17:13, Patrick Delaunay wrote:
Introduce STM32MP15 function and defines to prepare the
STM32MP13 introduction.
Signed-off-by: Patrick Delaunay
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/fdt.c | 123
1 file changed, 67 inser
Hi,
On 5/9/22 17:13, Patrick Delaunay wrote:
Add support of STM32MP13x the ETZPC part of fdt.c
Signed-off-by: Patrick Delaunay
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/fdt.c | 153 +++-
1 file changed, 151 insertions(+), 2 deletions(-)
A
Hi,
On 6/2/22 15:05, Patrick Delaunay wrote:
Add a directory in drivers/clk to regroup the clock drivers for all
STM32 SoCs with CONFIG_ARCH_STM32 (MCUs with Cortex-M) or
CONFIG_ARCH_STM32MP (MPUs with Cortex-A).
Signed-off-by: Patrick Delaunay
Reviewed-by: Grzegorz Szymaszek
Reviewed-by: Pat
Hi,
On 6/2/22 15:05, Patrick Delaunay wrote:
Add the MISC RCC driver for STM32MP13, and bind it to the RCC reset
driver, required for initial support.
Signed-off-by: Patrick Delaunay
Reviewed-by: Patrice Chotard
---
(no changes since v1)
drivers/misc/stm32_rcc.c | 6 ++
1 file change
Hi,
On 6/2/22 15:05, Patrick Delaunay wrote:
Add the RCC node, not yet in Linux kernel device tree
to handle the U-Boot RCC drivers with the needed U-Boot
property "u-boot,dm-pre-reloc" property as the clock and reset drivers
are required during pre-location.
Signed-off-by: Patrick Delaunay
R
Hi,
On 5/19/22 09:07, Patrick Delaunay wrote:
Replace gd->fdt_blob access with fdt_getprop() function to the
function ofnode_get_property() to support a live tree.
Signed-off-by: Patrick Delaunay
---
board/st/stm32mp1/stm32mp1.c | 13 -
1 file changed, 4 insertions(+), 9 deleti
Hi,
On 5/19/22 09:07, Patrick Delaunay wrote:
Replace gd->fdt_blob access with fdt_getprop() function to the
function ofnode_get_property() to support a live tree.
Signed-off-by: Patrick Delaunay
---
board/engicam/stm32mp1/stm32mp1.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions
Hi,
On 6/6/22 16:04, Patrick Delaunay wrote:
Replace call to fdt_*() functions and access to gd->fdt_blob
with call to ofnode_*() functions to support a live tree.
Tested-by: Marek Vasut
Signed-off-by: Patrick Delaunay
---
Changes in v1:
- previously sent as RFC, Tested by Marek
http://pa
Hi,
On 6/6/22 16:04, Patrick Delaunay wrote:
Activate the live DT with CONFIG_OF_LIVE to reduce the DT parsing
time.
Tested-by: Marek Vasut
Signed-off-by: Patrick Delaunay
---
Changes in v1:
- previously sent as RFC, Tested by Marek
http://patchwork.ozlabs.org/project/uboot/list/?series=3
Hi,
On 6/1/22 18:33, Patrick Delaunay wrote:
Depending on backup register value, U-Boot SPL maintains the debug unit
powered-on for debugging purpose; only BUCK1 is required for powering
the debug unit, so revert the setting for all the other power lanes,
except BUCK3 that has to be always on.
Hi,
On 6/15/22 19:41, Patrick Delaunay wrote:
Remove STM32_SYSRAM_END and clean the comments in stm32mp15_common.h file
after moving some CONFIG to Kconfig: CONFIG_SYS_CBSIZE,
CONFIG_SPL_MAX_FOOTPRINT, CONFIG_SYS_SPL_MALLOC_START and
CONFIG_SYS_SPL_MALLOC_SIZE.
Signed-off-by: Patrick Delaunay
Hi,
On 5/20/22 18:38, Patrick Delaunay wrote:
Replace reference to the correct name STMicroelectronics
Signed-off-by: Patrick Delaunay
---
arch/arm/Kconfig | 2 +-
arch/arm/cpu/armv7/stv0991/lowlevel.S | 2 +-
arch/arm/mach-sti/Kconfig | 2 +-
drivers/i2c
When 'ls' command is running with partition number, it's passed by a hex
value. For example, if want to check a 15th partition, it has to input
as 0xf.
Before applied
- ls mmc 0:f
After applied
- ls mmc 0:15
The using decimal number is more readable than passed by a hex value.
Signed-off-by: Jaeh
On 6/8/22 18:20, Stefan Herbrechtsmeier wrote:
[CAUTION: External Email]
From: Stefan Herbrechtsmeier
Add machine identification support based on the
zynqmp_get_silicon_idcode_name function in board/xilinx/zynqmp/zynqmp.c.
Signed-off-by: Stefan Herbrechtsmeier
---
drivers/soc/soc_xilin
On 6/8/22 18:20, Stefan Herbrechtsmeier wrote:
[CAUTION: External Email]
From: Stefan Herbrechtsmeier
Use the soc_get_machine function of the soc uclass to get silicon idcode
name for the fpga init.
Signed-off-by: Stefan Herbrechtsmeier
---
board/xilinx/zynqmp/zynqmp.c | 287 ++
The Google Chameleon v3 is a board made for testing both video and audio
interfaces of external devices. It has a connector compatible with the
Mercury+ AA1 module, which itself contains an Arria 10 SoCFPGA. The AA1
module comes in a few different configurations, the Chameleon V3 supports
ME-AA1-27
Devicetree headers for Mercury+ AA1 module
Signed-off-by: Paweł Anikiel
Reviewed-by: Simon Glass
---
.../socfpga_arria10_mercury_aa1-u-boot.dtsi | 54 ++
arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 72 +++
2 files changed, 126 insertions(+)
create mode 100644
Add handoff headers for the Google Chameleonv3 variants: 480-2 and
270-3. Both files were generated using qts-filter-a10.sh.
Signed-off-by: Paweł Anikiel
Reviewed-by: Simon Glass
---
...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305 ++
...ocfpga_arria10_chameleonv3_480_2_hand
Add devicetrees for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel
Signed-off-by: Alexandru M Stan
Reviewed-by: Simon Glass
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/socfpga_arria10_chameleonv3.dts | 90 +++
...fpga_arria10_chameleonv3_270_
Add board directory for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel
Reviewed-by: Simon Glass
---
board/google/chameleonv3/Makefile | 5 +++
board/google/chameleonv3/board.c | 27 ++
board/google/chameleonv3/fpga.its | 28 ++
board/
Add defconfig and Kconfig files for Google Chameleon V3 board
Signed-off-by: Paweł Anikiel
Reviewed-by: Simon Glass
---
arch/arm/mach-socfpga/Kconfig | 7 +
configs/socfpga_chameleonv3_defconfig | 29 ++
include/configs/socfpga_chameleonv3.h | 44 +++
>From the ATSHA204A datasheet (document DS40002025A):
Wake: If SDA is held low for a period greater than tWLO, the device
exits low-power mode and, after a delay of tWHI, is ready to receive
I2C commands.
tWHI value can be found in table 7-2.
Signed-off-by: Paweł Anikiel
Reviewed-by: Simon Glas
This driver is a child of the rstmgr driver, both of which share the
same devicetree node. As a result, passing the child's udevice pointer
to dev_read_addr_ptr results in a failure of reading the #address-cells
property. Use the parent udevice pointer instead.
Signed-off-by: Paweł Anikiel
Review
Using udelay while the clocks aren't fully configured causes the timer
system to save the wrong clock rate. Use sdelay and wait_on_value
instead (the values used in these functions were found experimentally).
Signed-off-by: Paweł Anikiel
---
arch/arm/mach-socfpga/clock_manager_arria10.c | 31 +++
Apply some optimizations to speed up bitstream loading
(both for full and split periph/core bitstreams):
* Change the size of the first fs read, so that all the subsequent
reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
This value was chosen so that in subsequent reads t
For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers be
Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).
Since commit 503eea451903 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
wit
Hi,
On 6/8/22 18:20, Stefan Herbrechtsmeier wrote:
[CAUTION: External Email]
From: Stefan Herbrechtsmeier
At the moment the xilinx zynqmp soc is only supported by xilinx vendor
boards. Rework the xilinx zynqmp board code to support reuse by foreign
vendor boards.
Stefan Herbrechtsmeier (10)
Hi Tom,
Please pull the STM32 related fixes for u-boot/master, v2022.07:
u-boot-stm32-20220617
- Fix the stm32prog command for stm32mp platform
- Add stm32mp15x DHCOR based DRC Compact board
CI status:
https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/12387
Thanks,
Patrick
Hi Etienne,
On 6/7/22 12:21, Etienne Carriere wrote:
Removes local variable child in optee_probe() that is not used.
Cc: Patrick Delaunay
Signed-off-by: Etienne Carriere
---
No change since v2.
New change not in v1 series.
---
drivers/tee/optee/core.c | 3 +--
1 file changed, 1 insertion(
Hi,
On 6/7/22 12:21, Etienne Carriere wrote:
This change defines resources for OP-TEE service drivers to register
themselves for being bound to when OP-TEE firmware reports the related
service is supported. OP-TEE services are discovered during optee
driver probe sequence which mandates optee dr
Hi,
On 6/7/22 12:21, Etienne Carriere wrote:
Changes optee_rng driver to register itself has a OP-TEE service so
that a device is bound for the driver when OP-TEE enumerates the
PTA RNG service.
Cc: Sughosh Ganu
Cc: Patrick Delaunay
Signed-off-by: Etienne Carriere
---
No change since v2.
No
Hi,
a minor remark
On 6/7/22 12:21, Etienne Carriere wrote:
Changes optee_rng driver to register itself has a OP-TEE service so
that a device is bound for the driver when OP-TEE enumerates the
PTA RNG service.
Cc: Sughosh Ganu
Cc: Patrick Delaunay
Signed-off-by: Etienne Carriere
---
No chan
On Fri, Jun 17, 2022 at 07:01:59PM +0900, Jaehoon Chung wrote:
> When 'ls' command is running with partition number, it's passed by a hex
> value. For example, if want to check a 15th partition, it has to input
> as 0xf.
> Before applied
> - ls mmc 0:f
> After applied
> - ls mmc 0:15
>
> The usin
On Fri, Apr 29, 2022 at 03:34:44PM +0200, Stefan Roese wrote:
> While working on an LX2160 based board and updating to latest mainline
> I noticed problems using the HW accelerated hash functions on this
> platform, when trying to boot a FIT Kernel image. Here the resulting
> error message:
>
>
On Sun, May 01, 2022 at 06:43:55PM +0200, Marek Vasut wrote:
> Replace discuss with discard, that is what happens with packet with
> incorrect checksum. Fix the typo.
>
> Fixes: 4b37fd146bb ("Convert CONFIG_UDP_CHECKSUM to Kconfig")
> Signed-off-by: Marek Vasut
> Cc: Ramon Fried
> Cc: Simon Gla
On Thu, May 12, 2022 at 08:21:01AM +0200, Christian Gmeiner wrote:
> Without this register unlock it is not possible to configure the
> pinmux used for mcu spi0.
>
> Fixes: 92e46092f2 ("arch: arm: mach-k3: am642_init: Probe ESM nodes")
> Signed-off-by: Christian Gmeiner
> Reviewed-by: Nishanth M
On Thu, May 12, 2022 at 04:21:53PM +0200, Christophe Leroy wrote:
> This patch updates my email address and company name.
>
> Signed-off-by: Christophe Leroy
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Tue, Jun 07, 2022 at 10:13:00AM +0200, Andrey Zhizhikin wrote:
> b4 utility [1] is introduced by Linux Kernel developers and used to
> fetch patches and patch series from lore.kernel.org and is proven
> to be useful for U-Boot development. Detailed usage of the tool can be
> read under post fro
On Wed, Jun 08, 2022 at 12:42:22AM +0100, Andre Przywara wrote:
> The generic EHCI binding does not *require* resets and clocks
> properties, and indeed for instance the Allwinner A20 SoCs does not
> need or define any resets in its DT.
>
> Don't easily give up if clk_get_bulk() or reset_get_bulk
On Wed, Jun 08, 2022 at 02:30:14PM -0400, Tom Rini wrote:
> When migrating CONFIG_CONS_INDEX to Kconfig, on this platform we changed
> what "board" evaluated to in the environment. This in turn meant that
> we would no longer try and find the correct fdtfile via the normal
> distro boot logic. F
On Thu, Jun 09, 2022 at 04:02:06PM +0200, Miquel Raynal wrote:
> Following Jincheng's report, an out-of-band write leading to arbitrary
> code execution is possible because on one side the squashfs logic
> accepts directory names up to 65535 bytes (u16), while U-Boot fs logic
> accepts directory n
On Sat, Jun 11, 2022 at 08:09:04AM +0200, Heiko Thiery wrote:
> With the move to use DM_CLK the boards uart stops working. The used
> properties are not supported by the imx8mq clock driver. Thus
> the correct baudrate cannot be selected. Remove this properties here and
> the board can start with
On Tue, Jun 14, 2022 at 12:11:10AM +0100, Andre Przywara wrote:
> Currently get_tcr() takes an "el" parameter, to select the proper
> version of the TCR_ELx system register.
> This is problematic in case of the Apple M1, since it runs with
> HCR_EL2.E2H fixed to 1, so TCR_EL2 is actually using the
On Tue, Jun 14, 2022 at 08:44:07AM +, Corentin LABBE wrote:
> The origin of this patch is the breaking of am335x-hs boot
> due to commit e41651fffda7 ("dm: Support parent devices with of-platdata")
> HS boards have less SRAM for SPL and so this commit increased memory usage
> beyond am335x li
On Tue, Jun 14, 2022 at 06:42:07PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan
>
> btool is needed after install binman to system.
>
> Signed-off-by: Peng Fan
> Reviewed-by: Alper Nebi Yasak
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On 6/9/22 14:30, Sughosh Ganu wrote:
From: Masami Hiramatsu
Add a section for the instruction of building the FWU Multi Bank
Update supported U-Boot and installation.
Signed-off-by: Masami Hiramatsu
Signed-off-by: Sughosh Ganu
---
doc/board/socionext/developerbox.rst | 110 +
On 6/9/22 14:30, Sughosh Ganu wrote:
From: Masami Hiramatsu
The DeveloperBox platform can support the FWU Multi bank
update. SCP firmware will switch the boot mode by DSW3-4
and load the Multi bank update supported TF-A BL2 from
0x60 offset on the SPI flash. Thus it can co-exist
with the
On 6/9/22 14:30, Sughosh Ganu wrote:
From: Masami Hiramatsu
Generate dfu_alt_info from the partition uuid information in the
devicetree, and record the mapping of partition uuid and the
index of dfu_alt_num.
This could be a reference implementation of the automatic DFU
generation for FWU mu
On Fri, Jun 17, 2022 at 12:31:56AM +0200, Francis Laniel wrote:
> Error messages like "unknown command" will make the CI fails.
> So, for the moment, we comment these tests.
>
> Signed-off-by: Francis Laniel
Why don't we have the test expect "unknown command" as the output here,
when on the new
Hi Patrick,
On Fri, 17 Jun 2022 at 14:06, Patrick DELAUNAY
wrote:
>
> Hi,
>
> a minor remark
>
> On 6/7/22 12:21, Etienne Carriere wrote:
> > Changes optee_rng driver to register itself has a OP-TEE service so
> > that a device is bound for the driver when OP-TEE enumerates the
> > PTA RNG servic
Hi Oleksandr,
Thank you for the follow-up.
I took the chance to test this patchset in the actual hardware. I
focused on the encrypted bitfiles (not authenticated) and I confirm it
works.
Regads,
Adrian
On 12.06.2022 00:06, Oleksandr Suvorov wrote:
This patchset introduces support for the a
On Fri, Jun 17, 2022 at 12:31:58AM +0200, Francis Laniel wrote:
> These boards used set_local_var() to store some variables as local shell.
> They then used get_local_var() to retrieve the variables values.
>
> Instead of using local shell variables, they should use environment ones
> (like a
>
On Fri, Jun 17, 2022 at 12:31:57AM +0200, Francis Laniel wrote:
> Signed-off-by: Francis Laniel
> ---
> test/cmd/setexpr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/test/cmd/setexpr.c b/test/cmd/setexpr.c
> index 0dc94f7e61..71c751d766 100644
> --- a/test/cmd/setex
On Fri, Jun 17, 2022 at 12:31:30AM +0200, Francis Laniel wrote:
> Hi.
>
>
> First I hope you are fine and the same for your relatives.
>
> During 2021 summer, Sean Anderson wrote a contribution to add a new shell,
> based
> on LIL, to U-Boot [1][2].
> While one of the goals of this contributio
Could you help us to get the DRAM part number which initialization failures on
the Rock Pi 4+.
We have found that some LPDDR4 abnormal operation at 50MHz.
I think you can try that use 400MHz to detect capacity.
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk33
Removes local variable child in optee_probe() that is not used.
Cc: Patrick Delaunay
Reviewed-by: Patrick Delaunay
Signed-off-by: Etienne Carriere
---
Changes since v3:
- Applied Patrick's R-b tag.
No change since v2.
New change not in v1 series.
---
drivers/tee/optee/core.c | 3 +--
1 file
This change defines resources for OP-TEE service drivers to register
themselves for being bound to when OP-TEE firmware reports the related
service is supported. OP-TEE services are discovered during optee
driver probe sequence which mandates optee driver is always probe once
bound.
Discovery of o
Changes optee_rng driver to register itself has a OP-TEE service so
that a device is bound for the driver when OP-TEE enumerates the
PTA RNG service.
Cc: Sughosh Ganu
Cc: Patrick Delaunay
Signed-off-by: Etienne Carriere
---
Changes since v3:
- Unconditionally register driver with OPTEE_SERVICE_
This patchset contains:
- i.MXRT1170 clock driver adaption
- i.MXRT1170-evk basic support
Jesse Taube (8):
imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK
ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header
dt-bindings: imx: Add clock binding for i.MXRT1170
clk: imx: Add i.
This commit adds board support for i.MXRT1170-EVK from NXP. This board
is an evaluation kit provided by NXP for i.MXRT117x processor family.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Nothing done
---
arch/arm/include/asm/arch-imx/cpu.h | 1 +
arch/arm/mach-imx/imxrt/Kconfig
Add the clock binding doc for i.MXRT1170.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Nothing done
---
include/dt-bindings/clock/imxrt1170-clock.h | 48 +
1 file changed, 48 insertions(+)
create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h
diff --git a/include/dt-
The i.MXRT11 series has two new pll types but are variants of existing.
This patch adds the ability to read one of the pll types' frequency
as it can't be changed unlike the generic pll it also has the
division factors swapped.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Change BM_PLL_POWER and BM
Add clock driver support for i.MXRT1170.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Use C file not dts for constant clock divider
---
drivers/clk/imx/Kconfig | 16 +++
drivers/clk/imx/Makefile| 1 +
drivers/clk/imx/clk-imxrt1170.c | 221
3 file
The i.MXRT11 series has different offsets for IOCR_MUX, it also can
address 64MiB of SDRAM so add a macro for that.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Nothing done
---
drivers/ram/imxrt_sdram.c| 9 +
include/dt-bindings/memory/imxrt-sdram.h | 1 +
2 files changed,
Add binding header for i.MXRT1170 pinctrl device tree.
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Nothing done
---
arch/arm/dts/imxrt1170-pinfunc.h | 1561 ++
1 file changed, 1561 insertions(+)
create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h
diff --git a/arch/ar
Add a base defconfig for the i.MXRT1170
Signed-off-by: Jesse Taube
---
V1 -> V2:
* Nothing done
---
configs/imxrt1170-evk_defconfig | 67 +
include/configs/imxrt1170-evk.h | 37 ++
2 files changed, 104 insertions(+)
create mode 100644 configs/imxr
The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MXRT, which features NXP's implementation of the Arm
Cortex-M7 and Cortex-M4 core.
The EVK provides 64 MB SDRAM, Micro SD card socket,
USB 2.0 OTG.
This patch aims to support the preliminary booting up featu
On Fri, 17 Jun 2022, c...@rock-chips.com wrote:
> Could you help us to get the DRAM part number which initialization failures
> on the Rock Pi 4+.
I have tested 3 boards; one appears to be fully working, on another 1
of the 2 LPDDR4 (Channel 1) chips consistently fails with a Col and
Cap Error
Hi,
These are few of the fixes picked up from U-boot tree done for
BeagleBone-AI64 and others.
Additional testing is much appreciated - my test environment is
currently limited :(
Nishanth Menon (3):
board: ti: common: Optimize boot when detecting consecutive bad
records
board: ti: commo
Due to supply chain issues, we are starting to see a mixture of eeprom
usage including the smaller 7-bit addressing eeproms such as 24c04
used for eeproms.
These eeproms don't respond well to 2 byte addressing and fail the
read operation. We do have a check to ensure that we are reading the
altern
The eeprom data area is much bigger than the data we intend to store,
however, with bad programming, we might end up reading bad records over
and over till we run out of eeprom space. instead just exit when 10
consecutive records are read.
Signed-off-by: Nishanth Menon
---
board/ti/common/board_
Do 1 byte address checks first prior to doing 2 byte address checks.
When performing 2 byte addressing on 1 byte addressing eeprom, the
second byte is taken in as a write operation and ends up erasing the
eeprom region we want to preserve.
While we could have theoretically handled this by ensuring
1 - 100 of 109 matches
Mail list logo
