This is the 5th version of patchset to add Intel N5X SoC[1] support.
Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in N5X are clock manager
and DDR subsystem, other IPs have minor changes compared to Agilex.
Intel N5X SoC supports legacy boot
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim
---
.../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8
include/configs/socfpga_soc64_common.h| 2 +-
Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when
OS booted from FIT image for Stratix 10 and Agilex. This flow is common for
all Intel SOC64 devices.
U-Boot will update 'fdt_addr' environment value based on FIT image in
board_prep_linux function, and 'linux_qspi_enable'
Reuse base_addr_soc64.h for Intel N5X device, the address is the
same as Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
b/arc
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-n5x.c | 489 ++
drivers/clk/altera/clk-n5x.h | 217 +++
From: Tien Fong Chee
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 38
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index f8d3d48ee8..9c19157de7 100644
--- a/arch/arm/mach-so
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-mem-n5x.c | 136 +++
drivers/clk/altera/clk-mem-n5x.h | 84 ++
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
arch/arm
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...{clock_manager_agilex.c => clock_manager_n5x.c} | 32 ++
arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 ++
.../mach-socfpga/include/mach/clock_manager_n5x.h | 12
3 files changed, 29 insertions
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
drivers/ddr/altera/sdram_soc64.c | 24 +---
1 fi
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 ++-
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/ar
From: Tien Fong Chee
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and use
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files changed, 9 insertion
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v5:
- Sort the node name in alphanumeric order in socfpga_n5x_socdk-u-boot.dtsi
- Remove duplicated qspi node from socfpga_n5x_socdk-u-boot.dtsi,
It is defined in socfpga_n5x_socdk.dtsi
v4:
- Reuse socfpg
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs/socf
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig | 21 +++-
arch/arm/mach-socfpga/Makefile | 28 ++
...lex_vab_defconfig => socfpga_n5x_atf_defco
Hi Marek,
On Sun, 2021-08-08 at 17:25 +0200, Marek Vasut wrote:
> Caution: EXT Email
>
> On 8/8/21 4:54 PM, Tom Rini wrote:
>
> [...]
>
> >
> > >
> > > >
> > > > I expect it was not simply because up
> > > > until rather recently we didn't have any checks for "don't
> > > > overwrite
> > > >
On 06/08/2021 15.38, Stefan Roese wrote:
> board_init_f_init_reserve() is called very early in the boot process,
> before the caches are enabled. Because of this, the optimized memset()
> version can't be used here on ARM64. With this patch, the simple memset
> version memset_simple() is used here
Returning fabricated CRS value (0x0001) by PCIe Root Complex to OS is
allowed only for 4-byte PCI_VENDOR_ID config read request and only when
CRSSVE bit in Root Port PCIe device is enabled. In all other error PCIe
Root Complex must return all-ones.
So implement this logic in pci-aardvark.c dri
Hi Peng,
On 07.08.21 10:00, Peng Fan (OSS) wrote:
From: Peng Fan
V5:
Rebased on latest master. The build break was introduced by Simon's
SPL config change that drop the "_SUPPORT". So this patchset
use new SPL config name in patch 44.
Thanks for fixing this. I am picking up the new ser
Hi Peter,
series was lost, sorry.
I have picked them up and rebased on current master. Anyway, build fails
(warning) due to
+board/warp7/warp7.c: In function 'board_eth_init':
+board/warp7/warp7.c:94:15: error: implicit declaration of function
'usb_eth_initialize'; did you mean 'sh_eth_initi
The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
which causes additional signal delay. At 108 MHz, this delay triggers
a sporadic issue where the first bit of RX data is not received by the
QSPI controller.
There are two options of addressing this problem, either by using the
The DHSOM SPI NOR is using 4k erase blocks, make use of it
and define the default environment sector size to 4k.
Signed-off-by: Marek Vasut
Cc: Patrice Chotard
Cc: Patrick Delaunay
---
configs/stm32mp15_dhcom_basic_defconfig | 2 +-
configs/stm32mp15_dhcor_basic_defconfig | 2 +-
2 files chang
Hi Marek
On 8/9/21 2:06 PM, Marek Vasut wrote:
> The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM,
> which causes additional signal delay. At 108 MHz, this delay triggers
> a sporadic issue where the first bit of RX data is not received by the
> QSPI controller.
>
> There are
Hi Marek
On 8/9/21 2:08 PM, Marek Vasut wrote:
> The DHSOM SPI NOR is using 4k erase blocks, make use of it
> and define the default environment sector size to 4k.
>
> Signed-off-by: Marek Vasut
> Cc: Patrice Chotard
> Cc: Patrick Delaunay
> ---
> configs/stm32mp15_dhcom_basic_defconfig | 2 +
On Mon, Aug 09, 2021 at 08:44:58AM +0200, Wolfgang Denk wrote:
> Dear Marek,
>
> In message <03720507-5ea4-0fb9-0549-37df3128b...@denx.de> you wrote:
> >
> > The IMX thing is odd indeed and raises a bigger question -- what is the
> > "right" amount of stack to reserve ?
>
> In the original U-Boo
21-08-04-assorted-minor-fixes' (2021-08-04 21:18:33
-0400)
are available in the Git repository at:
https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
tags/u-boot-imx-20210809
for you to fetch changes up to a8f46306413e2b47d1c93e45436ed11f5bb2c4c3:
imx: cmd: use struct cmd_tbl (
CONFIG_MMC_SPI_CRC_ON needs the crc16 functions, but it was not included
in an SPL build. For non-SPL builds, crc16.o is already added
unconditionally. This also removes CONFIG_SPL_YMODEM_SUPPORT from the
sifive board configs, which is only relevant for some ARM boards and was
only set for its si
On Mon, Aug 09, 2021 at 07:34:34AM +, Ye Li wrote:
> Hi Marek,
>
> On Sun, 2021-08-08 at 17:25 +0200, Marek Vasut wrote:
> > Caution: EXT Email
> >
> > On 8/8/21 4:54 PM, Tom Rini wrote:
> >
> > [...]
> >
> > >
> > > >
> > > > >
> > > > > I expect it was not simply because up
> > > > > u
Hi Rasmus,
On 09.08.21 09:52, Rasmus Villemoes wrote:
On 06/08/2021 15.38, Stefan Roese wrote:
board_init_f_init_reserve() is called very early in the boot process,
before the caches are enabled. Because of this, the optimized memset()
version can't be used here on ARM64. With this patch, the s
Dear Tom,
In message <20210809131640.GN858@bill-the-cat> you wrote:
>
> Thanks for explaining. It sounds like
> arch/arm/mach-imx/imx8m/soc.c::the=A0ft_system_setup() needs a comment
> that it uses a lot of stack, due to how complex it is, and that
I think this is the wrong approach. It sounds
On Mon, Aug 09, 2021 at 04:11:36PM +0200, Wolfgang Denk wrote:
> Dear Tom,
>
> In message <20210809131640.GN858@bill-the-cat> you wrote:
> >
> > Thanks for explaining. It sounds like
> > arch/arm/mach-imx/imx8m/soc.c::the=A0ft_system_setup() needs a comment
> > that it uses a lot of stack, due t
If ddr3_init() fails then DDR was not initialized and we cannot load and
execute U-Boot. We cannot continue, we cannot do anything in this case, so
hang.
Signed-off-by: Pali Rohár
---
arch/arm/mach-mvebu/spl.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach
On Thu, Aug 05, 2021 at 09:46:07AM -0600, Simon Glass wrote:
> Hi Heinrich,
>
> On Thu, 5 Aug 2021 at 09:29, Heinrich Schuchardt wrote:
> >
> >
> >
> > On 02.08.21 16:44, Simon Glass wrote:
> > > The changes to move from devicetree to rodata take things in the wrong
> > > direction for various r
On Mon, Aug 09, 2021 at 08:24:48AM +0200, Michal Simek wrote:
>
>
> On 8/6/21 8:46 PM, Tom Rini wrote:
> > On Fri, Aug 06, 2021 at 02:22:56PM +0200, Michal Simek wrote:
> >
> >> Based on DT spec you can have one memory node which multiple ranges or
> >> multiple nodes.
> >> fdt_fixup_memory_bank
On 8/7/21 9:24 AM, Simon Glass wrote:
This is actually a misnomer now, since the phandle info may contain
a driver_info index or a udevice index. Rename it to use the word
'phandle', which seems more accurate. Add a comment while we are here.
Also add a test for this function.
Signed-off-by:
On Sun, Aug 08, 2021 at 08:32:19PM -0600, Simon Glass wrote:
> Hi Tom,
>
> https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/8631
>
> The following changes since commit 8f07f5376a21a57ce191e5548b1a30c9709994d3:
>
> Merge tag 'video-2021-08-05' of
> https://source.denx.de/u-boot/c
t; The following changes since commit ab97eb341cb4fdbd69e33bd4a53714db95b5b63e:
>
> Merge branch '2021-08-04-assorted-minor-fixes' (2021-08-04 21:18:33 -0400)
>
> are available in the Git repository at:
>
> https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
>
On Sat, Aug 07, 2021 at 04:23:36PM -0600, Simon Glass wrote:
> Hi,
>
> U-Boot can be configured to build the source multiple times to product
> multiple
> 'phases'. The main phase is the full U-Boot, but an 'SPL' (Secondary Program
> Loader) build can produce a cut-down image only suitable for lo
Add u-boot,dm-spl tag in the pinmux device tree node, required for MMCSD1
subsystem.
Fixes: b6059ddc45b9 ("arm: dts: k3-am642: Add r5 specific dt support")
Signed-off-by: Aswath Govindraju
---
arch/arm/dts/k3-am642-evm-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/
On 8/7/21 6:23 PM, Simon Glass wrote:
Hi,
U-Boot can be configured to build the source multiple times to product multiple
'phases'. The main phase is the full U-Boot, but an 'SPL' (Secondary Program
Loader) build can produce a cut-down image only suitable for loading U-Boot
proper.
SPL does
Kojima-san,
On Fri, Aug 06, 2021 at 04:02:11PM +0900, Masahisa Kojima wrote:
> TCG PC Client PFP spec requires to measure the secure
> boot policy before validating the UEFI image.
> This commit adds the secure boot variable measurement
> of "SecureBoot", "PK", "KEK", "db", "dbx", "dbt", and "dbr"
On Fri, Aug 06, 2021 at 04:02:12PM +0900, Masahisa Kojima wrote:
> TCG PC Client PFP spec requires to measure "Boot"
> and "BootOrder" variables, EV_SEPARATOR event prior
> to the Ready to Boot invocation.
> Since u-boot does not implement Ready to Boot event,
> these measurements are performed
This is the 6th version of patchset to add Intel N5X SoC[1] support.
Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in N5X are clock manager
and DDR subsystem, other IPs have minor changes compared to Agilex.
Intel N5X SoC supports legacy boot
Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when
OS booted from FIT image for Stratix 10 and Agilex. This flow is common for
all Intel SOC64 devices.
U-Boot will update 'fdt_addr' environment value based on FIT image in
board_prep_linux function, and 'linux_qspi_enable'
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim
---
.../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8
include/configs/socfpga_soc64_common.h| 2 +-
Reuse base_addr_soc64.h for Intel N5X device, the address is the
same as Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
b/arc
From: Tien Fong Chee
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 38
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-n5x.c | 489 ++
drivers/clk/altera/clk-n5x.h | 217 +++
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index f8d3d48ee8..9c19157de7 100644
--- a/arch/arm/mach-so
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-mem-n5x.c | 136 +++
drivers/clk/altera/clk-mem-n5x.h | 84 ++
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
arch/arm
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...{clock_manager_agilex.c => clock_manager_n5x.c} | 32 ++
arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 ++
.../mach-socfpga/include/mach/clock_manager_n5x.h | 12
3 files changed, 29 insertions
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
drivers/ddr/altera/sdram_soc64.c | 24 +---
1 fi
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 ++-
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/ar
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files changed, 9 insertion
From: Tien Fong Chee
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and use
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs/socf
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v6:
- Sort the node name in alphanumeric order in socfpga_n5x_socdk-u-boot.dtsi
- Remove duplicated qspi node from socfpga_n5x_socdk-u-boot.dtsi,
It is defined in socfpga_n5x_socdk.dtsi
- Remove the incorr
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig | 21 +++-
arch/arm/mach-socfpga/Makefile | 28 ++
...lex_vab_defconfig => socfpga_n5x_atf_defco
On 8/3/21 12:44 AM, Zong Li wrote:
This driver is currently responsible for enabling all ccache ways.
Composable cache could be configure as RAM or cache, we will use it as
RAM at the beginning to put the u-boot SPL there. In u-boot proper
phrase, we will use the composable cache as cache, and tr
On 8/3/21 12:44 AM, Zong Li wrote:
Add an interface for cache initialization. Each platform can overwrite
this weak function by their own implementation, such as sifive_cache in
this patch.
Can we call this enable_caches instead of cache_init? This function is
called by initr_caches in board_r.
On 8/3/21 12:44 AM, Zong Li wrote:
Invokes the generic cache_enable interface to execute the relative
implementation in SiFive ccache driver.
Signed-off-by: Zong Li
---
arch/riscv/cpu/fu540/Kconfig | 1 +
arch/riscv/cpu/fu540/cache.c | 54 ++-
Re: [PATCH v2 5/6] riscv: lib: move platform-related libraries to sperate folder
nit: separate
On 8/3/21 12:44 AM, Zong Li wrote:
Put the platform-related implementation into their own folder
respectively. Just leave the common library in the top of lib
folder.
Signed-off-by: Zong Li
---
a
On 8/3/21 12:44 AM, Zong Li wrote:
We usually use a space in function declaration, rather than a tab.
Signed-off-by: Zong Li
---
arch/riscv/include/asm/cache.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
Cortina firmware currently supports non-tfa boot support and therefore
incorrect firmware address value is obtained. This patchset is an
attempt to fix cortina firmware.
LS2088A-RDB, T2080RDB and T4240RDB are also updated to incorporate
multiple firmware address values by extending a weak function
Add PHY_CORTINA as default option in SYS_MMC_ENV_DEV Kconfig entry as
PHY_CORTINA require SYS_MMC_ENV_DEV value similar to FMAN_ENET or QE.
This helps in resolving compilation failure.
Signed-off-by: Kuldeep Singh
---
env/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Use moveconfig.py script to convert below defines to Kconfig and move
these entries to defconfigs.
CONFIG_CORTINA_FW_ADDR
CONFIG_CORTINA_FW_LENGTH
Signed-off-by: Kuldeep Singh
---
configs/T2080RDB_NAND_defconfig | 1 +
configs/T2080RDB_SDCARD_defconfig | 1 +
Add support for boards supporting TFA boot separately in cortina
firmware. Please note, a weak function is defined to retrieve firmware
address values as CONFIG_CORTINA_FW_ADDR is now defined in defconfig and
can only have one possible value defined. This weak function will help
in overwrting the v
LS2088A-RDB supports TFA boot source and has 2 nor banks(default and
altbank) and QSPI as boot source. The corresponding defconfig can only
have one entry defined and therefore, extend cs4340_get_fw_addr()
function to overwrite firmware address which will be later used in
cortina firmware.
Signed-
T2080RDB supports booting from 2 nor banks(default and altbank). The
corresponding defconfig can only have one entry defined and therefore,
extend cs4340_get_fw_addr() function to overwrite firmware address which
will be later used in cortina firmware.
Signed-off-by: Kuldeep Singh
---
board/free
T4240RDB supports booting from 2 nor banks(default and altbank). The
corresponding defconfig can only have one entry defined and therefore,
extend cs4340_get_fw_addr() function to overwrite firmware address which
will be later used in cortina firmware.
Signed-off-by: Kuldeep Singh
---
board/free
Change maintainer to me. Eric no longer has this board and wishes
to see someone maintaining it actively.
Signed-off-by: Tony Dinh
---
board/Seagate/dockstar/MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/Seagate/dockstar/MAINTAINERS
b/board/Seagate/docks
On Tue, Aug 10, 2021 at 12:51 PM Sean Anderson wrote:
>
> On 8/3/21 12:44 AM, Zong Li wrote:
> > Invokes the generic cache_enable interface to execute the relative
> > implementation in SiFive ccache driver.
> >
> > Signed-off-by: Zong Li
> > ---
> > arch/riscv/cpu/fu540/Kconfig |
Change maintainer to me. Suriyan no longer has this board and wishes
to see someone maintaining it actively.
Signed-off-by: Tony Dinh
---
board/Seagate/goflexhome/MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/Seagate/goflexhome/MAINTAINERS
b/board/Seagat
On Tue, Aug 10, 2021 at 12:47 PM Sean Anderson wrote:
>
> On 8/3/21 12:44 AM, Zong Li wrote:
> > Add an interface for cache initialization. Each platform can overwrite
> > this weak function by their own implementation, such as sifive_cache in
> > this patch.
>
> Can we call this enable_caches ins
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