Hi Pali,
On 05.05.21 00:28, Pali Rohár wrote:
On Thursday 29 April 2021 11:00:17 Stefan Roese wrote:
Hi Marek,
(Added Tom and Simon to Cc)
On 29.04.21 10:27, Marek Behun wrote:
On Thu, 29 Apr 2021 08:46:36 +0200
Stefan Roese wrote:
phy: marvell: add RX training command
Applied to u
On Wed, May 05, 2021 at 05:02:21AM +0300, Ramon Fried wrote:
>
> On Mon, May 3, 2021 at 2:55 PM Ian Ray wrote:
> >
> > Calls made to eth_halt() by network operations (ping, nfs, tftp, etc.)
> > break netconsole if it is already running.
> >
> > * Maintain the network up / down state based on a re
Rename the misleading cmd "rx_training" to "mvebu_comphy_rx_training" to
avoid confusion and mixup with DDR3/4 training. This makes it clear,
that this command is platform specific and handles the COMPHY RX
training.
Also depend this cmd on ARMADA_8K and not TARGET_MVEBU_ARMADA_8K to make
is avail
When the PHY interface is set as TXID & RXID, the delays should be taken from
DT,
but first they should not be hardcoded since the PHY driver will set them.
Fixes: 798424e857 ("net: designware: add Amlogic Meson8b & later glue driver")
Signed-off-by: Neil Armstrong
---
drivers/net/dwmac_meson8b
Hi,
u-boot version: U-Boot 2021.07-rc1
Board: Beaglebone Black
I was trying to verify and use 'chpart' command on Beaglebone black with an
SDHC card ( with multiple partitions ) and am unable to get its exact
syntax.Is this command applicable to
any particular category of storage devices (viz. NO
From: Konstantin Porotchkin
This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN913x DB. This is only the base port with not all
interfaces supported fully.
Signed-off-by: Konstantin Porotchkin
Signed-off-by: Stefan Roese
---
Changes in v2:
- Changed commit text fro
This patchset adds the base support for the Marvell OcteonTX2 CN913x DB
board and includes required dts/dtsi files and the defconfig files for
this.
Thanks,
Stefan
Changes in v2:
- Changed commit text from CN9132 to CN913x as it supports all
variants
- Merge identical DT nodes from the A & B
From: Konstantin Porotchkin
This patch adds the base support for the Marvell Octeon TX2 CN913x DB.
Only one defconfig is added with this patch. Other board variants are
available (NAND, MMC booting) and images for these boards can be
generated by following the documentation added in the included
If the PHY isn't specified in the DT, -ENODATA means it should be skipped,
handle it like -ENOENT.
With that, devices without USB3 supported can have USB working (Odroid-HC4).
Fixes: adb049abf7 ("usb: dwc3: Add Meson G12A USB Glue")
Signed-off-by: Neil Armstrong
---
drivers/usb/dwc3/dwc3-meson-
On Wed, May 5, 2021 at 4:15 AM Green Wan wrote:
>
> Hi Dimitri,
>
> Thanks for looking into this.
>
> On Tue, May 4, 2021 at 5:33 PM Dimitri John Ledkov
> wrote:
> >
> > Hi,
> >
> > On Thu, Apr 22, 2021 at 10:15 AM Green Wan wrote:
> > >
> > > From: David Abdurachmanov
> > >
> > > Add fu740 sup
On Wednesday 05 May 2021 09:00:57 Stefan Roese wrote:
> Hi Pali,
>
> On 05.05.21 00:28, Pali Rohár wrote:
> > On Thursday 29 April 2021 11:00:17 Stefan Roese wrote:
> > > Hi Marek,
> > >
> > > (Added Tom and Simon to Cc)
> > >
> > > On 29.04.21 10:27, Marek Behun wrote:
> > > > On Thu, 29 Apr 20
In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", the second byte is the
inverse of the opcode.
Hi,
This series adds support for octal DTR flashes in the SPI NOR framework,
and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA
flashes.
The Cadence QSPI controller driver is also updated to run in Octal DTR
mode.
Tested on TI J721E for MT35XU512ABA and J7200 for S28HS512T. Al
Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 3 +++
include/spi-mem.h | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index c
Controllers can use this function to perform basic sanity checking on
the spi-mem op.
Reviewed-by: Sean Anderson
Signed-off-by: Pratyush Yadav
---
include/spi-mem.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/spi-mem.h b/include/spi-mem.h
index fe249f77ba..de3c11c8e2 100644
-
spi_mem_default_supports_op() rejects DTR ops by default to ensure that
the controller drivers that haven't been updated with DTR support
continue to reject them. It also makes sure that controllers that don't
support DTR mode at all (which is most of them at the moment) also
reject them.
This mea
If the device tree provides a read delay value, use that directly and do
not perform the calibration procedure.
This allows the device tree to over-ride the read delay value in cases
where the read delay value obtained via calibration is incorrect. One
such example is the Cypress Semper flash. It
Once the start bit is toggled it takes a small amount of time before it
is internally synchronized. This means we can't start writing during
that part. So add a small delay to allow the bit to be synchronized.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 4
drivers/spi
Set up opcode extension and enable/disable DTR mode based on whether the
command is DTR or not.
xSPI flashes can have a 4-byte dummy address associated with some
commands like the Read Status Register command in octal DTR mode. Since
the flash does not support sending the dummy address, we can not
The SPI NOR core will get Octal DTR in following commits. This has
presented a significant challenge of keeping the SPL size in check on
the x530 platform.
On a previous iteration of the series, adding a set of compile-time
switches got the build working. But rebasing on the latest master breaks
t
If a flash chip has more than 16MB capacity but its BFPT reports
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
The check in spi_nor_scan() doesn't catch it because addr_width did get
set. This fixes that check.
Ported from Kernel commit 324f78dfb442b82365548b657ec4e6974c6
nor->setup() can be used by flashes to configure settings in case they
have any peculiarities that can't be easily expressed by the generic
spi-nor framework. This includes things like different opcodes, dummy
cycles, page size, uniform/non-uniform sector sizes, etc.
Move related declarations to a
These structures will be used in a later commit inside another structure
definition. Also take the declarations out of the ifdef since they won't
affect the final binary anyway and will be used in a later commit.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 224
Sometimes the information in a flash's SFDP tables is wrong. Sometimes
some information just can't be expressed in the SFDP table. So,
introduce the fixup hooks to allow tailoring settings for a specific
flash.
Three hooks are added: default_init, post_sfdp, and post_bfpt. These
allow tweaking the
Even when spi_nor_write_reg() has no data to write, like when executing
a write enable operation, it sets the data direction to
SPI_MEM_DATA_OUT. This trips up spi_mem_check_buswidth() because it
expects a data phase when there is none. Make sure the data direction is
set to SPI_MEM_NO_DATA when th
The spi-mem layer provides a spi_mem_supports_op() function to check
whether a specific operation is supported by the controller or not.
This is much more accurate than the hwcaps selection logic based on
SPI_{RX,TX}_ flags.
Rework the hwcaps selection logic to use spi_mem_supports_op().
To make
Double Transfer Rate (DTR) is SPI protocol in which data is transferred
on each clock edge as opposed to on each clock cycle. Make
framework-level changes to allow supporting flashes in DTR mode.
Right now, mixed DTR modes are not supported. So, for example a mode
like 4S-4D-4D will not work. All
JESD216 rev D makes BFPT 20 DWORDs. Update the BFPT size define to
reflect that.
The check for rev A or later compared the BFPT header length with the
maximum BFPT length, BFPT_DWORD_MAX. Since BFPT_DWORD_MAX was 16, and so
was the BFPT length for both rev A and B, this check worked fine. But
now,
Some devices in DTR mode expect an extra command byte called the
extension. The extension can either be same as the opcode, bitwise
inverse of the opcode, or another additional byte forming a 16-byte
opcode. Get the extension type from the BFPT. For now, only flashes with
"repeat" and "inverse" ext
This table is indication that the flash is xSPI compliant and hence
supports octal DTR mode. Extract information like the fast read opcode,
the number of dummy cycles needed for a Read Status Register command,
and the number of address bytes needed for a Read Status Register
command.
The default d
Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 31 +++
include/linux/mtd/spi-nor.h| 2 ++
2 files changed, 33 insertions(
The xSPI Profile 1.0 table specifies how many dummy cycles and address
bytes are needed for the Read Status Register command in Octal DTR mode.
Use that information to send the correct Read SR command.
Some controllers might have trouble reading just 1 byte in DTR mode. So,
when we are in DTR mode
The Micron MT35XU512ABA flash does not support the quad enable bit. But
instead of programming the Quad Enable Require field to 000b ("Device
does not have a QE bit"), it is programmed to 111b ("Reserved").
While this is technically incorrect, it is not reason enough to abort
BFPT parsing. Instead
A Soft Reset sequence will return the flash to Power-on-Reset (POR)
state. It consists of two commands: Soft Reset Enable and Soft Reset.
Find out if the sequence is supported from BFPT DWORD 16.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 6 ++
include/linux/mtd/spi-n
On probe, the SPI NOR core will put a flash in 8D-8D-8D mode if it
supports it. But Linux as of now expects to get the flash in 1S-1S-1S
mode. Handing the flash to Linux in Octal DTR mode means the kernel will
fail to detect the flash.
So, we need to reset to Power-on-Reset (POR) state before hand
When the flash is handed to us in a stateful mode like 8D-8D-8D, it is
difficult to detect the mode the flash is in. One option is to read SFDP
in all modes and see which one gives the correct "SFDP" signature, but
not all flashes support SFDP in 8D-8D-8D mode.
Further, even if you detect the mod
On devices with non-uniform sector sizes like Spansion S25 or S28 family
of flashes the sector under erase does not necessarily have to be
mtd->erasesize bytes long. For example, on S28 flashes the first 128 KiB
region is composed of 32 4 KiB sectors, then a 128 KiB sector, and then
256 KiB sectors
From: Takahiro Kuwano
Some of Spansion/Cypress chips have overlaid 4KB sectors at top and/or
bottom, depending on the device configuration, while U-Boot supports
uniform sector layout only.
The spansion_erase_non_uniform() erases overlaid 4KB sectors,
non-overlaid portion of normal sector, and
The Cypress Semper flash is an xSPI compliant octal DTR flash. Add
support for using it in octal DTR mode.
The flash by default boots in a hybrid sector mode. Switch to uniform
sector mode on boot. Use the default 20 dummy cycles for a read fast
command.
The SFDP programming on some older version
Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.
Signed-off-by: Pratyush Yadav
--
On 5/5/21 10:41 AM, Neil Armstrong wrote:
If the PHY isn't specified in the DT, -ENODATA means it should be skipped,
handle it like -ENOENT.
With that, devices without USB3 supported can have USB working (Odroid-HC4).
Shouldn't you rather specify NOP PHY in the DT ?
Hi, Stefan,
I think the MAINTAINERS file should be fixed for reflecting the configuration
file name change and moving to single defconfig from 2.
Regards
Kosta
From: Stefan Roese
Sent: Wednesday, May 5, 2021 11:21
To: u-boot@lists.denx.de
Cc: Kostya Por
Just an update.
I wrote a test stub, and I did not find any issue with the current u-boot
implementation regarding this command underrun issue.
However, for some unknown reasons, our AST2400/AST2500 u-boot builds had the
command buffer underrun issue that the cursor can be moved back into the
Adding new DH electronics mailing list and myself as a maintainer.
Signed-off-by: Christoph Niedermaier
---
board/dhelectronics/dh_imx6/MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/dhelectronics/dh_imx6/MAINTAINERS
b/board/dhelectronics/dh_imx6/MAINTAINERS
index ab4e1
Adding new DH electronics mailing list.
Signed-off-by: Christoph Niedermaier
---
board/dhelectronics/dh_stm32mp1/MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/dhelectronics/dh_stm32mp1/MAINTAINERS
b/board/dhelectronics/dh_stm32mp1/MAINTAINERS
index fd70131f9e..9ce21c3ab2
Unit addresses are not allowed anymore in a FIT image since
commit 3f04db891a35 ("image: Check for unit addresses in FITs")
This caused this error on mkimage creation:
./tools/mkimage: verify_header failed for FIT Image support with exit code 1
Makefile:1393: recipe for target 'u-boot.itb' faile
fdt_getprop_u32_default_node() promises to take the "cell" number into
account when returning the value of a property array.
However it actually misses out on this, always returning the first cell
only instead. This was so far not a problem, since every user always
asks for cell 0.
Observe the in
Xilinx TFA is normally placed to OCM at 0xfffea000 with a max size of 88kB.
By adding new and new features to TFA this split is reaching its limit
that there would be a need to change structures a little bit.
The idea is to resort SPL (potentially also Xilinx first stage bootloader
FSBL) that the b
All newer Allwinner SoCs (since about 2013) miss the CONFIGDATA register
in their MUSB implementation, so they need a quirk to hardcode this.
Currently this quirk depends on listing the SoCs affected in musb_reg.h,
which means that this list needs to grow with every new chip.
Move the quirk featu
Most clock factors and dividers in the H6 PLLs use a "+1 encoding",
which we were missing on two occasions.
This fixes the MMC clock setup on the H6, which could be slightly off due
to the wrong parent frequency:
mmc 2 set mod-clk req 5200 parent 117600 n 2 m 12 rate 4900
Also the CPU
Hi Simon,
On Thu, Apr 29, 2021 at 7:10 PM Simon Glass wrote:
>
> Hi Igor,
>
> On Fri, 16 Apr 2021 at 01:10, Igor Opaniuk wrote:
> >
> > From: Igor Opaniuk
> >
> > Introduce RSA_SOFTWARE_EXP_TINY Kconfig option, which does not require
> > DM to be enabled. This can be handy on devices, where SPL
Board designed for quick prototyping and has one microSD port,
2 Ethernet ports, 2 USB ports, I2C, SPI, CAN, RS-485, GPIO,
UART interfaces, and 2 RGB LEDs.
Signed-off-by: Oleh Kravchenko
---
MAINTAINERS | 10 +
arch/arm/dts/Makefile |
A simple prototyping board with one microSD port, one Ethernet port,
2 USB ports, I2C, SPI, GPIO, and UART interfaces.
Signed-off-by: Oleh Kravchenko
---
MAINTAINERS | 2 +
arch/arm/dts/Makefile| 3 +
arch/arm/dts/ev-imx280-nano-x-mb.
The H616 is our first supported Allwinner SoC which goes beyond the 4GB
address space "barrier", by having more than 32 address bits.
Lift the preliminary 3GB DRAM limit for the H616, and update the page
table setup on the way, to actually map that last GB as well.
As not all devices are actually
Hello Oliver,
> -Original Message-
> From: U-Boot On Behalf Of Oliver Graute
> Sent: Wednesday, May 5, 2021 2:01 PM
> To: sba...@denx.de
> Cc: feste...@gmail.com; peng@nxp.com;
> oliver.gra...@kococonnector.com; u-boot@lists.denx.de; Simon Glass
> ; uboot-imx
> Subject: [PATCH v1] im
This series updates binman to handle creation of u-boot.itb image for
RISC-V SiFive Unleashed board.
QEMU RISC-V remains unchanged, as binman uses a dtb to describe the
image format, but for QEMU RISC-V there is no dtb as dtb is passed
to U-Boot via CONFIG_OF_PRIOR_STAGE.
Not sure how such use ca
It should be FDT, not FTD.
Signed-off-by: Bin Meng
---
common/Kconfig.boot | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/Kconfig.boot b/common/Kconfig.boot
index 5a18d62d78..94d82c27dd 100644
--- a/common/Kconfig.boot
+++ b/common/Kconfig.boot
@@ -204,7 +204,7 @@ co
It needs a space around '-a'.
Signed-off-by: Bin Meng
---
tools/binman/binman.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst
index 1aa2459d50..b3df3a6428 100644
--- a/tools/binman/binman.rst
+++ b/tools/binman/binman
This is wrongly referring to Intel ME, which should be ATF.
Signed-off-by: Bin Meng
---
tools/binman/etype/atf_bl31.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/binman/etype/atf_bl31.py b/tools/binman/etype/atf_bl31.py
index 163d714184..2041da416c 100644
--- a/to
Currently there are 2 binman test cases using the same 172 number.
It seems that 172_fit_fdt.dts was originally named as 170_, but
commit c0f1ebe9c1b9 ("binman: Allow selecting default FIT configuration")
changed its name to 172_ for no reason. Let's change it back.
Signed-off-by: Bin Meng
---
It should be 171_fit_fdt_missing_prop.dts.
Signed-off-by: Bin Meng
---
tools/binman/ftest.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 08f84cd32d..b0daccbc3b 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest
Add an entry for RISC-V OpenSBI's 'fw_dynamic' firmware payload.
Signed-off-by: Bin Meng
---
tools/binman/entries.rst | 13 +
tools/binman/etype/opensbi.py | 23 +++
tools/binman/ftest.py | 7 +++
tools/binman/test/201_opensbi.dts |
When using binman to generate an FIT image, these intermediate files
"*.fit.fit" and "*.fit.itb" are generated from mkimage, which should
be cleaned, and git ignored.
While we are here, clean the map file generated by "binman -m" as well.
Signed-off-by: Bin Meng
---
.gitignore | 4 +++-
Makefi
This updates the make rules to pass OpenSBI blob to binman.
Signed-off-by: Bin Meng
---
Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/Makefile b/Makefile
index a5701f6f9a..c1ddcae22d 100644
--- a/Makefile
+++ b/Makefile
@@ -1287,6 +1287,7 @@ cmd_binman = $(srctree)/tools/binman/b
At present SiFive Unleashed board uses the Makefile to create the FIT,
using USE_SPL_FIT_GENERATOR, which is deprecated as per the Makefile
warning. Update to use binman instead.
Signed-off-by: Bin Meng
---
arch/riscv/dts/binman.dtsi| 70 +++
.../dts/hifive-
On 5/5/21 2:51 PM, Andre Przywara wrote:
All newer Allwinner SoCs (since about 2013) miss the CONFIGDATA register
in their MUSB implementation, so they need a quirk to hardcode this.
Currently this quirk depends on listing the SoCs affected in musb_reg.h,
which means that this list needs to grow
Hi Priyanka,
These changes have been tested and validated .
If no comments, please merge them . Ethernet changes for RevC boards has
dependency on this patch.
Regards,
Wasim
> -Original Message-
> From: Wasim Khan
> Sent: Saturday, April 17, 2021 11:34 PM
> To: Priyanka Jain ; Varun S
Adding new DH electronics mailing list and update list of maintainers.
Signed-off-by: Christoph Niedermaier
---
V2: Correct message tag and update list of maintainers
---
board/dhelectronics/dh_imx6/MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/dhelectro
Adding new DH electronics mailing list.
Signed-off-by: Christoph Niedermaier
---
V2: Correct message tag
---
board/dhelectronics/dh_stm32mp1/MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/dhelectronics/dh_stm32mp1/MAINTAINERS
b/board/dhelectronics/dh_stm32mp1/MAINTAINERS
On Wed, 5 May 2021 11:19:13 +0200
Pali Rohár wrote:
> > "bubt" is special and cannot be changed easily without breaking update
> > scripts using it AFAICT. As it's pretty old and used in the Marvell code
> > base for quite some time - including all the documentation about
> > updating.
>
> I s
On Wed, 5 May 2021 09:15:10 +0200
Stefan Roese wrote:
> Rename the misleading cmd "rx_training" to "mvebu_comphy_rx_training" to
> avoid confusion and mixup with DDR3/4 training. This makes it clear,
> that this command is platform specific and handles the COMPHY RX
> training.
>
> Also depend
On 5/4/21 11:58 AM, Simon Glass wrote:
Hi Alex,
On Thu, 29 Apr 2021 at 10:10, Simon Glass wrote:
Hi Alex,
On Mon, 26 Apr 2021 at 07:21, Alex G. wrote:
On 4/23/21 11:56 PM, Simon Glass wrote:
Hi Tom, Alex,
On Fri, 23 Apr 2021 at 12:47, Tom Rini wrote:
On Fri, Apr 23, 2021 at 11:5
Hello,
Resurrecting this series; v2 [1] was sort of put on hold due to some org
changes at TI. Sorry about the delay caused by this.
Anyways, v3 is mostly just a rebase of this series on top of
2021.07-rc1, and addition of some new data to support new boot modes for
j721e and j7200. This series h
From: Tero Kristo
Copy the best rational approximation calculation routines from Linux.
Typical usecase for these routines is to calculate the M/N divider
values for PLLs to reach a specific clock rate.
This is based on linux kernel commit:
"lib/math/rational.c: fix possible incorrect result fro
From: Tero Kristo
On J7 family of SoCs (J721E and J7200), sysfw is being split to be run
under two cores, TIFS portion on DMSC core, and DM firmware under MCU
R5. As MCU R5 is also used to run one phase of the bootloader, we must
prevent access from here towards sysfw services. To support this, a
From: Tero Kristo
With the sysfw rearch, sysfw PM calls are no longer available from SPL
level. To properly support this, remove the is_on checks and the reset
assertion from the R5 remoteproc driver as these are not supported.
Attempting to access unavailable services will cause the device to ha
From: Lokesh Vutla
board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.
Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
Signed-off-by: Tero Kristo
---
arc
From: Tero Kristo
Some clocks are not associated to a DM node, so just parsing the DM is not
enough. This is especially true for root clocks, which typically don't have
any parents. Instead, fetch every registered UCLASS_CLK instance, and dump
these out.
Signed-off-by: Tero Kristo
Signed-off-by
From: Tero Kristo
Bail out early if device returned for the parent clock is null.
This avoids warning prints like this when doing clk dump:
dev_get_uclass_priv: null device
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/clk-uclass.c | 2 ++
1 file changed, 2 insertio
From: Tero Kristo
Current driver only supports registering fixed rate clocks from DT. Add
new API which makes it possible to register fixed rate clocks directly
from e.g. platform specific clock drivers.
Reviewed-by: Peng Fan
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/
From: Tero Kristo
If a clock provider is not ready for assigning default rates/parents
during its probe, it may return -EPROBE_DEFER directly from xlate.
Handle this special case properly by skipping the entry and adjusting the
return value to pass. The defaults will be handled properly in post p
From: Tero Kristo
Add new clk subcommand "clk setfreq", for setting up a clock rate
directly from u-boot cmdline. This is handy for any debugging purposes
towards clocks.
Acked-by: Lukasz Majewski
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
cmd/clk.c | 49 ++
From: Tero Kristo
Clock rates are cached within the individual clock nodes, and right now
if one changes a clock rate somewhere in the middle of the tree, none
of its child clocks notice the change. To fix this, clear up all the
cached rates for us and our child clocks.
Signed-off-by: Tero Krist
From: Tero Kristo
Set rate should return the new clock rate on success, and negative error
value on failure. Fix this, as currently set_rate returns 0 on success.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/ti/clk-sci.c | 6 --
1 file changed, 4 insertions(+), 2
From: Tero Kristo
Add support for TI K3 SoC PLLs. This clock type supports
enabling/disabling/setting and querying the clock rate for the PLL. The
euclidean library routine is used to calculate divider/multiplier rates
for the PLLs.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
dr
From: Tero Kristo
Add support command for debugging K3 power domains. This is useful with
the HSM rearch setup, where power domains are directly controlled by SPL
instead of going through the TI SCI layer. The debugging support is only
available in the u-boot codebase though, so the raw register
From: Tero Kristo
Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/config.mk | 4
tools
From: Tero Kristo
Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting this.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/power/domain/Kconfig
From: Tero Kristo
Add driver to support TI K3 generation SoC clocks. This driver registers
the clocks provided via platform data, and adds support for controlling
the clocks via DT handles.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
drivers/clk/ti/Kconfig | 12 ++
drivers/clk
From: Tero Kristo
Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/common.c | 80 +
arch/arm/mach-k3/com
From: Tero Kristo
If the raw PM support is built in, we are operating in the split
firmware approach mode where RM and PM support is not available. In this
case, skip the board config for these two.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/sysfw-loader.c | 4
From: Dave Gerlach
Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/common.c | 7 ---
1 file changed, 4 insertions(
From: Tero Kristo
Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
arch/a
From: Dave Gerlach
Force the clk-k3 driver to probe early during R5 SPL boot to ensure the
default system clock configuration is completed. Many other drivers
assume a default state of the clock tree and it is currently possible
for them to probe before clk-k3 depending on the exact system
config
From: Dave Gerlach
Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/Makefile | 2 +-
ar
From: Tero Kristo
Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
configs/j721e_evm_r
From: Dave Gerlach
Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.
Signed-off-by: Dave Gerlach
Signed-off-by: Tero Kristo
---
configs/j7200_evm
From: Tero Kristo
Update build instructions and image formats based on HSM rearch. A new
DM image is added into the build, which gets executed right after R5
SPL finishes its job.
Signed-off-by: Tero Kristo
Signed-off-by: Tero Kristo
---
board/ti/j721e/README | 9 ++---
1 file changed, 6
MCU timer1 is used as the tick timer for MCU R5 SPL, and the
clock-frequency defined in DT appears to be incorrect at the moment.
Actual clock source for the timer is MCU_SYSCLK0 / 4 which is 250MHz.
Earlier setup of 25MHz went unnoticed, as there was a separate issue
with omap-timer, which caused
Uhm,
Sorry for CC:ing a stale email address with the patches, t-kri...@ti.com
is no longer functional. Please drop that from any of the replies if you
don't fancy spam replies from server.
-Tero
On 05/05/2021 20:55, Tero Kristo wrote:
Hello,
Resurrecting this series; v2 [1] was sort of put
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