Hi Tom,
Hope you are well, I have a question regarding one of my patches pending for
ACK:
https://patchwork.ozlabs.org/project/uboot/list/?series=&submitter=80669&state=&q=&archive=&delegate=
Is it possible to get some attention on my questions, the changes are deep in
arm generic code and mayb
On 29.04.21 14:03, Dagan Martinez wrote:
From c200095d4136a071dd9526a48be642ce58fae8c9 Mon Sep 17 00:00:00 2001
From: Dagan Martinez
Date: Tue, 27 Apr 2021 15:48:31 -0400
Subject: [PATCH v2] Kirkwood: Fix tv sec/usec normalization in kwboot
`kwboot.c` had an issue where it failed to normalize
This is the 2nd version of patchset to add Intel N5X SoC[1] support.
Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in N5X are clock manager
and DDR subsystem, other IPs have minor changes compared to Agilex.
Intel N5X SoC supports legacy boot
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim
---
.../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8
include/configs/socfpga_soc64_common.h| 2 +-
2 files changed
Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when
OS booted from FIT image for Stratix 10 and Agilex. This flow is common for
all Intel SOC64 devices.
U-Boot will update 'fdt_addr' environment value based on FIT image in
board_prep_linux function, and 'linux_qspi_enable'
Reuse base_addr_soc64.h for Intel N5X device, the address is the
same as Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
b/arc
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v2:
- Enabled auto detect the endianness from the magic word
- Merged and simpl
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 64a7c9d652..9305bec38a 100644
--- a/arch/arm/mach-so
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim
---
v2:
- common.h need to be included before clock_manager.h
- Remove unnecessary comment : write 1 to clear
- Remove unnecessary () in the code
---
drivers/clk/altera/Makefile
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
v2:
- common.h need to be included before clock_manager.h
- For consistency, use small letter fo 0x0c and 0x1c in macros
---
drivers/clk/altera/Makefile |
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...k_manager_agilex.c => clock_manager_n5x.c} | 32 +--
.../mach-socfpga/include/mach/clock_manager.h | 2 ++
.../include/mach/clock_manager_n5x.h | 12 +++
3 files changed, 29 insertions(+), 17 deletions(-
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
arch/arm
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
v2:
- Renamed local variable “total_size” to “remaining_size”
---
d
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
.../mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 +++
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/arch/arm/m
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v2:
- Remove socfpga_n5x.dtsi
- Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update
n5x data accordingly.
---
arch/arm/dts/Makefile | 1 +
...ex-u-boot.dtsi => socfpga_
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
.../{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files changed, 9 insertions(+
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from tool.
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs/socfpga_n5x_
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
v2:
- Move linux_qspi_enable from bootcommand
---
arch/arm/mach-socfpga/Kconfig | 21 +-
arch/arm/mach-socfpga/Makefile| 28 +++
...ab_def
Hi Heinrich,
pá 1. 1. 2021 v 19:29 odesílatel Heinrich Schuchardt
napsal:
>
> Implement services OpenEx(), ReadEx(), WriteEx(), FlushEx() of the
> EFI_FILE_PROTOCOL.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> include/efi_api.h | 28 ++--
> lib/efi_loader/efi_file.c | 317 ++
On 30.04.21 12:09, Michal Simek wrote:
> Hi Heinrich,
>
> pá 1. 1. 2021 v 19:29 odesílatel Heinrich Schuchardt
> napsal:
>>
>> Implement services OpenEx(), ReadEx(), WriteEx(), FlushEx() of the
>> EFI_FILE_PROTOCOL.
>>
>> Signed-off-by: Heinrich Schuchardt
>> ---
>> include/efi_api.h |
In SquashFS, the contents of a directory is stored by
squashfs_directory_entry structures which contain the file's name, inode
and position within the filesystem.
The inode number is not stored directly; instead each directory has one
or more headers which set a base inode number, and files store
From: MengLi
In latest u-boot code, watchdog feature is implemented, so enable
wdt command by default.
Signed-off-by: Meng Li
---
configs/socfpga_stratix10_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/socfpga_stratix10_defconfig
b/configs/socfpga_stratix10_defconfig
i
From: MengLi
In uboot command line environment, watchdog is not able to be
stopped with below commands:
SOCFPGA_STRATIX10 # wdt dev watchdog@ffd00200
SOCFPGA_STRATIX10 # wdt stop
Refer to watchdog driver in linux kernel, it is also need to reset
watchdog after disable it so that the disable actio
On Thu, Apr 29, 2021 at 04:16:02PM -0700, Simon Glass wrote:
> Hi Tom,
>
> https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/7344
>
>
> The following changes since commit 79b0f08d6af498e6fda8cd257d62e2095764410c:
>
> configs: Resync with savedefconfig (2021-04-27 08:28:38 -0400)
Hi,
We now see the first Allwinner devices [1] having DRAM located above
4GB in address space (4GB DRAM starting at 1GB). After one fix[2]
this works somewhat fine, but the sun8i-emac network device is still
limited to 32-bit DMA addresses. With U-Boot relocating itself (plus
stack and heap) to th
pá 30. 4. 2021 v 12:42 odesílatel Heinrich Schuchardt
napsal:
>
> On 30.04.21 12:09, Michal Simek wrote:
> > Hi Heinrich,
> >
> > pá 1. 1. 2021 v 19:29 odesílatel Heinrich Schuchardt
> > napsal:
> >>
> >> Implement services OpenEx(), ReadEx(), WriteEx(), FlushEx() of the
> >> EFI_FILE_PROTOCOL.
>
Currently the code sets eth1addr only if /ethernet1 alias exists in DT,
the node pointed to by the alias has "micrel,ks8851-mll" compatible
string, and the KSZ8851 CCR register read indicates programmed EEPROM
is not connected.
This is not sufficient to detect cases where the DT still contains the
st 28. 4. 2021 v 15:22 odesílatel Peng Fan (OSS) napsal:
>
> From: Peng Fan
>
> This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
> but that fix was wrongly partial reverted.
>
> When reading a directory, EFI_BUFFER_TOO_SMALL should be returned when
> the supplied buffer
The CMD_UNZIP provides the 'gzwrite' command, which is convenient
for writing e.g. gz-compressed images to eMMC from U-Boot.
Signed-off-by: Marek Vasut
Cc: Patrice Chotard
Cc: Patrick Delaunay
---
configs/stm32mp15_dhcom_basic_defconfig | 1 +
configs/stm32mp15_dhcor_basic_defconfig | 1 +
2 f
On Fri, Feb 19, 2021 at 09:46:49PM +, Aleksandar Gerasimovski wrote:
> This is a draft patch to describe the problem and to initiate
> a discussion for solution.
>
> PRAM usage is not taken into account when reserving lmb for ARM
> architecture, this means that predefined PRAM region is reser
> Date: Fri, 30 Apr 2021 12:21:21 +0100
> From: Andre Przywara
>
> Hi,
>
> We now see the first Allwinner devices [1] having DRAM located above
> 4GB in address space (4GB DRAM starting at 1GB). After one fix[2]
> this works somewhat fine, but the sun8i-emac network device is still
> limited to
Hi All,
Please find invite for next TF-A Tech Forum session to continue our discussions
on HOB implementation, feel free to forward it to others.
The next TF-A Tech Forum is scheduled for Thu 6th May 2021 16:00 – 17:00 (BST).
Agenda:
* Discussion Session: Static and Dynamic Information
'dma-ranges' frequently exists without parent nodes having 'dma-ranges'.
While this is an error for 'ranges', this is fine because DMA capable
devices always have a translatable DMA address. Also, with no
'dma-ranges' at all, the assumption is that DMA addresses are 1:1 with
no restrictions unless
In of_get_address(), there is:
dev_count_cells(dev, &na, &ns);
followed by:
bus->count_cells(dev, &na, &ns);
but no codes in between use na/ns, hence the first call is useless.
By dropping the first call, dev_count_cells() is now useless too.
Signed-off-by: Bin Meng
---
Changes in v2:
-
This patchset adds some Kirkwood SPI driver patches from the Marvell
SDK. This is needed to resolve some issues with correct SPI NOR
operation on the CN9132 DB board.
Thanks,
Stefan
Grzegorz Jaszczyk (1):
spi: kirkwood: prevent limiting speed to 0
Ken Ma (1):
spi: kirkwood: support extend
From: Ken Ma
The Armada SoC family implementation of this SPI hardware module has
extended the configuration register to allow for a wider range of SPI
clock rates. Specifically the Serial Baud Rate Pre-selection bits in the
SPI Interface Configuration Register now also use bits 6 and 7 as well.
From: Grzegorz Jaszczyk
After commit 1fe929ed497bcc8975be8d37383ebafd22b99dd2
("spi: kirkwood: prevent configuring speed exceeding max controller freq")
the spi frequency could be set to 0 on platform where spi-max-frequency
is not defined (e.g. on armada-388-gp). Prevent limiting speed in
mentio
From: Marcin Wojtas
This patch adds a limitation in the kirkwood_spi driver
set_speed hook, which prevents setting too high transfer
speed.
Signed-off-by: Marcin Wojtas
Reviewed-by: Kostya Porotchkin
Tested-by: Kostya Porotchkin
Signed-off-by: Stefan Roese
---
drivers/spi/kirkwood_spi.c |
This patchset adds some Armada8k MMU setup related patches from the
Marvell SDK. This is needed to resolve some PCI related issues that I
exprienced while porting mainline U-Boot to the CN9132 DB board.
Thanks,
Stefan
Grzegorz Jaszczyk (3):
arm64: mvebu: do not map firmware RT service region
From: jinghua
1. RAM: base address 0x0 size 2Gbytes
2. MMIO: base address 0xf000 size 1Gbytes
Signed-off-by: Ofir Fedida
Signed-off-by: Stefan Roese
---
arch/arm/mach-mvebu/armada8k/cpu.c | 62 --
1 file changed, 7 insertions(+), 55 deletions(-)
diff --git a/
From: Grzegorz Jaszczyk
There is region left by ATF, which needs to remain in memory to provide RT
services. To prevent overwriting it by u-boot, do not provide any mapping
for this memory region, so any attempt to access it will trigger
synchronous exception.
Update sr 2021-04-12:
Don't update
From: Grzegorz Jaszczyk
Some of the setups including cn9130 opens mmio window starting from
0xc000, reflect it in the u-boot code.
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Kostya Porotchkin
Signed-off-by: Stefan Roese
---
arch/arm/mach-mvebu/armada8k/cpu.c | 4 ++--
arch/
From: Grzegorz Jaszczyk
Signed-off-by: Grzegorz Jaszczyk
Signed-off-by: Stefan Roese
---
arch/arm/mach-mvebu/include/mach/fw_info.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-mvebu/include/mach/fw_info.h
b/arch/arm/mach-mvebu/include/mach/fw_info.h
index ab2bb91bd5b
From: Marcin Wojtas
The pcie_dw_mvebu configure ATU regions for memory, configuration
and IO space types. However the latter is not obligatory
and when not specified in the device tree, causes wrong
ATU configuration. Fix that by adding a dependency on the
detected PCIE regions count.
Signed-off
On Fri, 30 Apr 2021 14:02:52 +0200 (CEST)
Mark Kettenis wrote:
Hi Mark,
thanks for the reply!
(CC:ing Alex and Heinrich for the UEFI questions below)
> > Date: Fri, 30 Apr 2021 12:21:21 +0100
> > From: Andre Przywara
> >
> > Hi,
> >
> > We now see the first Allwinner devices [1] having DRAM
On Fri, Apr 30, 2021 at 7:40 AM Stefan Roese wrote:
>
> On 29.04.21 22:24, Ramon Fried wrote:
> > On Tue, Apr 27, 2021 at 4:28 PM Stefan Roese wrote:
> >>
> >> From: Ben Peled
> >>
> >> Signed-off-by: Ben Peled
> >> Reviewed-by: Stefan Chulski
> >> Reviewed-by: Kostya Porotchkin
> >> Tested-b
On 4/30/21 1:26 AM, meng...@windriver.com wrote:
> From: MengLi
>
> In uboot command line environment, watchdog is not able to be
> stopped with below commands:
> SOCFPGA_STRATIX10 # wdt dev watchdog@ffd00200
> SOCFPGA_STRATIX10 # wdt stop
> Refer to watchdog driver in linux kernel, it is also
Hi!
Dne petek, 30. april 2021 ob 15:34:28 CEST je Andre Przywara napisal(a):
> On Fri, 30 Apr 2021 14:02:52 +0200 (CEST)
> Mark Kettenis wrote:
>
> Hi Mark,
>
> thanks for the reply!
>
> (CC:ing Alex and Heinrich for the UEFI questions below)
>
> > > Date: Fri, 30 Apr 2021 12:21:21 +0100
> >
Hi Masami,
On Thu, 29 Apr 2021 at 20:03, Masami Hiramatsu
wrote:
>
> Hi Simon,
>
> 2021年4月30日(金) 1:10 Simon Glass :
> >
> > Hi Masami,
> >
> > On Fri, 16 Apr 2021 at 16:38, Masami Hiramatsu
> > wrote:
> > >
> > > Many architecture do not have specific asm/arch/gpio.h, so instead
> > > of adding
Hi Bin,
On Thu, 29 Apr 2021 at 17:01, Bin Meng wrote:
>
> Hi Simon,
>
> On Fri, Apr 30, 2021 at 12:10 AM Simon Glass wrote:
> >
> > Hi Bin,
> >
> > On Sun, 25 Apr 2021 at 18:21, Bin Meng wrote:
> > >
> > > Hi Simon,
> > >
> > > On Sun, Apr 25, 2021 at 10:10 AM Simon Glass wrote:
> > > >
> > >
Hi,
On Thu, 29 Apr 2021 at 17:11, Bin Meng wrote:
>
> On Sat, Apr 24, 2021 at 8:57 PM Marek Vasut wrote:
> >
> > On 2/25/21 9:50 PM, Marek Vasut wrote:
> > > In case binman is enabled, the u-boot.itb is generated using this tool
> > > and there is no direct u-boot.itb target, but instead the bin
On Fri, 30 Apr 2021 at 07:17, Bin Meng wrote:
>
> In of_get_address(), there is:
>
> dev_count_cells(dev, &na, &ns);
>
> followed by:
>
> bus->count_cells(dev, &na, &ns);
>
> but no codes in between use na/ns, hence the first call is useless.
> By dropping the first call, dev_count_cells() is
On Fri, Apr 30, 2021 at 9:14 PM Simon Glass wrote:
> On Thu, 29 Apr 2021 at 17:01, Bin Meng wrote:
> > On Fri, Apr 30, 2021 at 12:10 AM Simon Glass wrote:
> > > On Sun, 25 Apr 2021 at 18:21, Bin Meng wrote:
> > > > On Sun, Apr 25, 2021 at 10:10 AM Simon Glass wrote:
> > > > > On Sun, 25 Apr 20
On 4/30/21 8:13 PM, Simon Glass wrote:
Hi,
Hello Simon,
On Thu, 29 Apr 2021 at 17:11, Bin Meng wrote:
On Sat, Apr 24, 2021 at 8:57 PM Marek Vasut wrote:
On 2/25/21 9:50 PM, Marek Vasut wrote:
In case binman is enabled, the u-boot.itb is generated using this tool
and there is no direct
Hi Marek,
On Fri, 30 Apr 2021 at 11:47, Marek Vasut wrote:
>
> On 4/30/21 8:13 PM, Simon Glass wrote:
> > Hi,
>
> Hello Simon,
>
> > On Thu, 29 Apr 2021 at 17:11, Bin Meng wrote:
> >>
> >> On Sat, Apr 24, 2021 at 8:57 PM Marek Vasut wrote:
> >>>
> >>> On 2/25/21 9:50 PM, Marek Vasut wrote:
> >>
Hi Marek
Can you resend this patch to our @foss.st.com email address please ?
Thanks
Patrice
De : Marek Vasut
Envoyé : vendredi 30 avril 2021 13:49
À : u-boot@lists.denx.de
Cc : Marek Vasut ; Patrice CHOTARD ;
Patrick DELAUNAY
Objet : [PATCH] ARM: stm32: Enabl
Hi Marek
Can you resend this patch to our @foss.st.com email address please ?
Thanks
Patrice
De : Marek Vasut
Envoyé : vendredi 30 avril 2021 13:29
À : u-boot@lists.denx.de
Cc : Marek Vasut ; Patrice CHOTARD ;
Patrick DELAUNAY
Objet : [PATCH] ARM: stm32: Add a
Hi Simon,
On Sat, May 1, 2021 at 2:14 AM Simon Glass wrote:
>
> On Fri, 30 Apr 2021 at 07:17, Bin Meng wrote:
> >
> > In of_get_address(), there is:
> >
> > dev_count_cells(dev, &na, &ns);
> >
> > followed by:
> >
> > bus->count_cells(dev, &na, &ns);
> >
> > but no codes in between use na/ns
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