Hi Bin,
On Wed, 3 Mar 2021 at 14:54, Simon Glass wrote:
>
> On Fri, 26 Feb 2021 at 00:36, Bin Meng wrote:
> >
> > The implementation of of_translate_one() was taken from the one in
> > Linux kernel drivers/of/address.c, and the Linux one added a quirk
> > for Apple Macs that don't have the prop
HI Heinrich,
On Thu, 11 Feb 2021 at 10:34, Simon Glass wrote:
>
> On Wed, 10 Feb 2021 at 10:59, Heinrich Schuchardt wrote:
> >
> > UEFI test files like helloworld.efi require an architecture specific
> > PE-COFF header.
> >
> > Currently this does not work for cross compiling. If $CROSS_COMPILE
Hi Alexandru,
On Wed, 10 Mar 2021 at 11:04, Alexandru Gagniuc wrote:
>
> spl_load_fit_image() will try to load an image at the address given
> in the "load" property. Absent such property, it uses
>
> image_info->load_addr
>
> Correct use of this is demonstrated in spl_fit_append_fdt(), w
Hi Alexandru,
On Wed, 10 Mar 2021 at 11:04, Alexandru Gagniuc wrote:
>
> The FPGA loading code in spl_simple_fit_read() can easily be separated
> from the rest of the logic. It is split into two functions instead of
> one because spl_fit_upload_fpga() is used in a subsequent patch.
>
> Signed-off
Extracting files to the current directory is not normally a very friendly
thing to do, but it can be warranted, e.g. in a new temporary dir. At
present binman reports an error when such an attempt is made. Fix it.
Signed-off-by: Simon Glass
---
(no changes since v1)
tools/binman/control.py | 2
U-Boot's various phase binaries actually comprise two or three pieces.
For example, u-boot.bin has the executable followed by a devicetree.
With binman we want to be able to update that devicetree with full image
information so that it is accessible to the executable. This is tricky
if it is not c
Move the documentation to the base method as it is with other methods.
Also update it a little while we are here.
Signed-off-by: Simon Glass
---
(no changes since v1)
tools/binman/entry.py | 11 +++
tools/binman/etype/section.py | 6 --
2 files changed, 11 insertions(+), 6
Regenerate the entry documentation, which step was missed when the
files-align feature was added.
Fixes: 6eb9932668f ("binman: Support alignment of files")
Signed-off-by: Simon Glass
---
(no changes since v1)
tools/binman/README.entries | 1 +
1 file changed, 1 insertion(+)
diff --git a/tool
Several entries currently use an underscore in the entry-type name, but in
fact a hyphen is used. Update the docs to fix this as it might be
confusing.
Also simplify the 'filename' comment and fix the 'operation' typo.
Signed-off-by: Simon Glass
---
(no changes since v1)
tools/binman/README.e
The documentation for this entry indicates that the SPL binary is included
along with the padding. It is not, so update it to correct the error.
Signed-off-by: Simon Glass
---
(no changes since v1)
tools/binman/README.entries | 17 ++---
tools/binman/etype/u_boot_spl_b
Allow this entry type to be placed in an image. This is the TPL binary,
without a devicetree appended.
Signed-off-by: Simon Glass
---
(no changes since v1)
tools/binman/README.entries| 14 +++
tools/binman/etype/u_boot_tpl_nodtb.py | 27 ++
tools
This entry holds the padding between the end of of TPL binary and the
end of BSS. This region must be left empty so that the devicetree can be
appended correctly and remain accessible without interfering with BSS.
Signed-off-by: Simon Glass
---
(no changes since v1)
tools/binman/README.entries
As the first step in supporting expanded entries, add a way for binman to
automatically select an 'expanded' version of an entry type, if requested.
This is controlled by a class method.
Signed-off-by: Simon Glass
---
(no changes since v1)
tools/binman/entry.py | 60 ++
Add a new command-line option to disable expanded entries. This is needed
for most tests, since it is much easier to 'factor out' this function into
a separate test and keep the existing packing tests simple.
Add the option and select it by default from tests.
Signed-off-by: Simon Glass
---
(no
Add support for this feature in the control, image and section modules, so
that expanded entries will be selected by default. So far there are no
expanded entry types, so this is a nop.
Signed-off-by: Simon Glass
---
(no changes since v1)
tools/binman/control.py | 24 ++--
To support the use of 'expanded' entries, binman needs to be told whether
SPL and TPL have a devicetree and whether they need BSS padding. Add these
to the Makefile.
Signed-off-by: Simon Glass
---
(no changes since v1)
Makefile | 8
1 file changed, 8 insertions(+)
diff --git a/Makefi
When creating an entry, check for an expanded version of that entry, then
use it instead. This allows, for example use of:
u-boot {
};
instead of having to write out in full:
u-boot {
type = "section";
u-boot-nodtb {
};
u-boot-dtb {
};
};
Add an imple
We don't need to spell out the separate pieces of U-Boot phase binaries
anymore. Revert to using the simple entry and let binman do the expansion
itself as needed.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/dts/u-boot.dtsi | 11 +--
1 file changed, 1 insertion(+), 10
This cannot be used since the previous #elif has already dealt with SPL.
Drop it.
Signed-off-by: Simon Glass
---
(no changes since v1)
arch/x86/dts/u-boot.dtsi | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 501
Much of the content here is useful only for development. Move it under
that section.
Signed-off-by: Simon Glass
---
Changes in v2:
- Move UEFI under develop/ instead
doc/develop/index.rst| 1 +
doc/{ => develop}/uefi/index.rst | 4
doc/{ => develop}/uefi/iscs
These docs are useful for developers, not users. Move them under that
section.
Suggested-by: Heinrich Schuchardt
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch to move driver model docs under develop/
doc/{ => develop}/driver-model/bind.rst | 0
doc/{ => develop}
Collect the material into different top-level headings to make it easier
to read.
Signed-off-by: Simon Glass
---
(no changes since v1)
tools/binman/binman.rst | 523
1 file changed, 266 insertions(+), 257 deletions(-)
diff --git a/tools/binman/binman.r
Update this to avoid sphinx warnings and incorporate it into the new
documentaiton tree.
Signed-off-by: Simon Glass
---
(no changes since v1)
tools/binman/cmdline.py | 2 +-
tools/binman/{README.entries => entries.rst} | 79 +++-
tools/binman/etype/cbfs.py
A few sections are a little out of date now. Update them.
Signed-off-by: Simon Glass
---
(no changes since v1)
tools/binman/binman.rst | 83 ++---
1 file changed, 44 insertions(+), 39 deletions(-)
diff --git a/tools/binman/binman.rst b/tools/binman/binman.r
Add a link to binman's documentation and adjust the files so that it is
accessible. Use the name README.rst so it is easy to discover when binman
is installed without U-Boot.
Signed-off-by: Simon Glass
---
Changes in v2:
- Put binman docs in doc/develop and FIT in doc/usage
- Rename README.rst t
Many entries start 'Entry containing a'. This looks fine in the source
code but is annoying when viewed in the htmldocs table of contents. Drop
these unnecessary words.
Signed-off-by: Simon Glass
---
(no changes since v1)
tools/binman/entries.rst| 76 ++---
Hi Tom
Please pull the STM32 related patches for u-boot/master, v2021.07:
u-boot-stm32-20210312
CI status: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/6732
he following changes since commit c5219c4a18f2b27547ecd799914f94e48b0fa86f:
Prepare v2021.04-rc3 (2021-03-01 22:46:
Hi Simon,
> Il 15/03/2021 04:01 Simon Glass ha scritto:
>
>
> Hi Dario,
>
> On Wed, 30 Dec 2020 at 12:08, Dario Binacchi wrote:
> >
> > We can handle the sysc interconnect target module in a generic way for
> > many TI SoCs. Initially let's just enable domain clocks before the
> > children a
Move Stratix10 and Agilex SPL common code to spl_soc64.c.
We are in preparation for new n5x device support.
No functional change in this patch.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 2 ++
arch/arm/mach-socfpga/spl_agilex.c | 16
arch/arm/mach-soc
On Thu, Mar 11, 2021 at 4:45 PM Bin Meng wrote:
>
> On Thu, Mar 11, 2021 at 10:42 PM Green Wan wrote:
> >
> >
> >
> > Bin Meng 於 2021年3月11日 週四，下午10:22寫道：
> >>
> >> On Thu, Mar 11, 2021 at 9:50 PM Green Wan wrote:
> >> >
> >> > Add fu740 support to macb ethernet driver
> >> >
> >> > Signed-off-by
On 3/11/21 11:55 PM, Robert Hancock wrote:
> The code was trying to disable PCS auto-negotiation when a fixed-link node
> is present and enable it otherwise. However, the PCS registers were being
> written before the PCSSEL bit was set in the network configuration
> register, and it appears that
Hi Tom,
Please find the PR for master branch targeted for v2021.04-rc4 release.
Details about the PR are updated in the tag message.
Gitlab build report:
https://source.denx.de/u-boot/custodians/u-boot-ti/-/pipelines/6767
The following changes since commit ad7e1c7c6e2bde2b369f10984d41d6b
On 06/03/21 8:18 am, Adam Ford wrote:
> In a previous attempt to unify config options and remove items
> from the whitelist file, SPL items were moved into a section
> enabled with CONFIG_SPL_BUILD. Unfortunately, SPL_PAD_TO
> is referenced at the head Makefile and uses this define
> to create
On 13/03/21 9:04 pm, Adam Ford wrote:
> On Thu, Mar 4, 2021 at 10:32 AM Adam Ford wrote:
>>
>> With bd_info dropped from the data section, the Logic PD OMAP3 boards
>> and AM3517 fail to boot. Enabling CONFIG_SPL_ALLOC_BD restores
>> them.
>>
>> Fixes: 38d6b7ebdaee ("spl: Drop bd_info in the da
On Fri, 12 Mar 2021 15:47:12 -0500
Tom Rini wrote:
> On Fri, Mar 12, 2021 at 06:36:05PM +0100, Marek Behun wrote:
> > On Fri, 12 Mar 2021 18:19:08 +0100
> > Heinrich Schuchardt wrote:
> >
> > > On 12.03.21 18:03, Marek Behun wrote:
> > > > On Fri, 12 Mar 2021 08:34:41 -0800
> > > > Tim Harv
This patchset is extracted from "Add Intel Diamond Mesa SoC support" series.
We are in preparation to support new Intel N5X (Diamond Mesa) SOC64 device
and we would like to clean up some code before enable N5X device.
This patchset restructure Stratix10 and Agilex handoff code to be
generic and t
Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from
S10_HANDOFF to SOC64_HANDOFF.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/clock_manager_s10.c | 2 +-
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39 --
arch/arm/mach-socfpga/inc
Rename to common file name to used by all SOC64 devices.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile| 4 ++--
.../mach-socfpga/{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} | 0
2 files changed, 2 insertions(+), 2 deletions(-)
r
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile| 4 ++--
.../arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c} | 0
2 files changed, 2 inserti
Rearrange sequence of macros in handoff_soc64.h without any functionality
change. In preparation for Stratix10 and Agilex handoff function
restructuring.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 22 --
1 file changed, 12 insertions
Restructure Stratix10 and Agilex handoff code to used by
all SOC64 devices, in preparation to support handoff for
Diamond Mesa.
Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c
which contains the generic function to parse the handoff
data.
Update system_manager_soc64.c to use generic han
On 14.03.21 20:04, Mark Kettenis wrote:
> The devicetree specification clearly states that:
>
> As with the /reserved-memory node, when booting via UEFI
> entries in the Memory Reservation Block must also be listed
> in the system memory map obtained via the GetMemoryMap() toi
> protect aga
Hi Mark!
On Sat, 2021-03-13 at 10:24 +0100, Mark Kettenis wrote:
[...]
> Fortunately Nicolas Saenz Julienne recently introduced
> dev_phys_to_bus() and dev_bus_to_phys() interfaces to do this. Those
> interfaces make use of a dma-ranges property in the device tree which
> doesn't work so well for
First check if there is an alias for the device tree node defined with the
given num before checking against device index.
Signed-off-by: Aswath Govindraju
---
drivers/mmc/mmc.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
inde
The following series of patches,
- add support to check for a device with a sequence number equal to device
number before looking for matching index
- assign device number based on node's alias index in SPL too.
Aswath Govindraju (2):
mmc: Check for device with a seq number equal to num befor
Assign the nodes alias index as the device number in SPL too, if
CONFIG_SPL_DM_SEQ_ALIAS is enabled.
Signed-off-by: Aswath Govindraju
---
drivers/mmc/mmc-uclass.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
in
On 3/15/21 6:11 AM, Simon Glass wrote:
Move this documentation over to reST. Move the example files into a files/
directory so they are still separate.
Do a few minor updates while we are here:
- Tidy up sandbox build instructions
- Update my github account name
- Add some talks and links
Signe
On 3/15/21 6:11 AM, Simon Glass wrote:
This can crash if the EC has not yet been probed. Add a check to prevent
What does 'This' relate to? There seems a sentence to missing from the
commit message.
Best regards
Heinrich
this.
Signed-off-by: Simon Glass
---
drivers/misc/cros_ec_sandbox
This series contains various patches related to running U-Boot with
Chromium OS verified boot. Most of them relate to sandbox.
Simon Glass (19):
sandbox: Only call timer_timebase_fallback() if present
sandbox: Only delete the executable if requested
sandbox: cros_ec: Only write EC state whe
On Thu, Feb 11, 2021 at 04:40:09PM +0200, Andy Shevchenko wrote:
> On some distributions the mkfs.ext4 is under /sbin and /sbin is not set
> for mere users. Include /sbin to the PATH when creating ext4 disk image,
> so that users won't get a scary traceback from Python.
It has been a long. Is it
This patchset is extracted from "Add Intel Diamond Mesa SoC support" series.
We are in preparation to support new Intel N5X (Diamond Mesa) SOC64 device
and we would like to clean up some code before enable N5X device.
This patchset move duplicated function 'cm_get_qspi_controller_clk_hz' to
clock_
Changed to store QSPI reference clock in kHz instead of Hz in
boot scratch cold0 register for Stratix10 and Agilex.
This patch is in preparation for Intel N5X SDRAM driver
support. Reserved 4 bits for Intel N5X SDRAM driver,
and there will be 28 bits to store QSPI reference clock.
Due to limited b
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/clock_manager.c | 15 ---
arch/arm/mach-socfpga/clock_manager_agilex.c | 6 --
arch/arm/mac
+Dario Binacchi
On Mon, Mar 15, 2021 at 3:11 PM Simon Glass wrote:
>
> Hi Bin,
>
> On Wed, 3 Mar 2021 at 14:54, Simon Glass wrote:
> >
> > On Fri, 26 Feb 2021 at 00:36, Bin Meng wrote:
> > >
> > > The implementation of of_translate_one() was taken from the one in
> > > Linux kernel drivers/of/a
commit e58e68d9 ("mmc: mtk-sd: assign plat->cfg.f_max with a correct value")
wrongly assumed that plat->cfg.f_max is always unset at the time
mscd_drv_probe() is run. This is not true in case max-frequency being
defined in device tree, as it is then already set by mmc_of_parse()
in msdc_of_to_plat(
Hello everyone,
In mxs_nand_spl.c:nand_spl_load_image, if a bad block is found it should
supposedly loop until a good block is found. However is_badblock() is
called with the same offset over and over. Is this a bug or am I missing
something here?
/* * Check if we have crossed a block bounda
The purpose of this series is to allow booting an OP-TEE image from
SPL, by corectly configuring the TrustZone (TZC) memory regions.
Although TZC400 is a generic silicon logic that could apply to other
mach- families, support is currently restricted to stm32mp. I have
neither a feasible way nor in
In general, Falcon mode means we're booting a linux kernel directly.
With FIT images, however, an OP-TEE secure kernel can be booted before
linux. Thus, if the next stage is an IH_OS_TEE, this isn't necessarily
a problem.
Of course, a general solution would involve mmc_load_image_raw_os()
only loa
OP-TEE requires some particular setup, which is not needed for linux
or other payloads. Add a hook for platform-specific code to perform
any OP-TEE related configuration and initialization.
A weak function is used because it is symmetrical to other
spl_board_prepare_for_*() implementations. A solu
Add the "/reserved-memory/optee" node to the SPL devicetree. The
purpose is to allow configuring TZC regions when booting OP-TEE.
Signed-off-by: Alexandru Gagniuc
---
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/stm32mp157a-dk1-u-bo
The purpose of this change is to allow configuring TrustZone (TZC)
memory permissions. For example, OP-TEE expects TZC regions to be
configured in a very particular way. The API presented here is
intended to allow exactly that.
UCLASS support is not implemented, because it would not be too useful.
OP-TEE is very particular about how the TZC should be configured.
When booting an OP-TEE payload, an incorrect TZC configuration will
result in a panic.
Most information can be derived from the SPL devicetree. The only
information we don't have is the split between TZDRAM and shared
memory. This h
On Wed, Jan 20, 2021 at 08:10:52PM -0700, Simon Glass wrote:
> At present only a single flag (force_debug) is used in log records. Before
> adding more, convert this into a bitfield, so more can be added without
> using more space.
>
> To avoid expanding the log_record struct itself (which some d
On Wed, Jan 20, 2021 at 08:10:53PM -0700, Simon Glass wrote:
> When multiple log() calls are used which don't end in newline, the
> log prefix is prepended multiple times in the same line. This makes the
> output look strange.
>
> Fix this by detecting when the previous log record did not end in
On Wed, Jan 20, 2021 at 08:10:54PM -0700, Simon Glass wrote:
> The existing log_ret() and log_msg_ret() macros consider an error to be
> less than zero. But some function may return a positive number to indicate
> a different kind of failure. Add macros to check for that also.
>
> Signed-off-by:
On Wed, Jan 20, 2021 at 08:10:56PM -0700, Simon Glass wrote:
> We don't need to enable logging to run this command since the output will
> still appear. Drop the 'select'.
>
> Signed-off-by: Simon Glass
Applied to u-boot/next, thanks!
--
Tom
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Description: PGP signature
On Sun, Feb 07, 2021 at 02:27:04PM -0700, Simon Glass wrote:
> Fix the warning:
>
> drivers/tpm/tpm2_tis_sandbox.c: In function ‘sandbox_tpm2_xfer’:
> drivers/tpm/tpm2_tis_sandbox.c:288:48: warning: format ‘%ld’ expects
> argument of type ‘long int’, but argument 2 has type ‘size_t’
>
On Sun, Feb 07, 2021 at 02:27:05PM -0700, Simon Glass wrote:
> Some format strings use the wrong type. Fix them.
>
> Example warnings:
>
> In file included from test/dm/acpi.c:22:
> test/dm/acpi.c: In function ‘dm_test_acpi_cmd_list’:
> test/dm/acpi.c:362:21: warning: format ‘%lx’ expects argume
On Sun, Feb 07, 2021 at 02:27:07PM -0700, Simon Glass wrote:
> The 'reset' command now resets sandbox but does not quit it. Fix the
> instructions.
>
> Fixes: 329dccc0675 ("sandbox: implement reset")
> Signed-off-by: Simon Glass
Applied to u-boot/next, thanks!
--
Tom
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Descripti
On Sun, Feb 14, 2021 at 04:27:23PM +0100, Jorge Ramirez-Ortiz wrote:
> This Trusted Application allows enabling SCP03 as well as provisioning
> the keys on TEE controlled secure element (ie, NXP SE050).
>
> All the information flowing on buses (ie I2C) between the processor
> and the secure eleme
On Sun, Feb 14, 2021 at 04:27:24PM +0100, Jorge Ramirez-Ortiz wrote:
> Enable and provision the SCP03 keys on a TEE controlled secured elemt
> from the U-Boot shell.
>
> Executing this command will generate and program new SCP03 encryption
> keys on the secure element NVM.
>
> Depending on the T
On Sun, Feb 14, 2021 at 04:27:25PM +0100, Jorge Ramirez-Ortiz wrote:
> Adds support for a working SCP03 emulation. Input parameters are
> validated however the commands (enable, provision) executed by the TEE
> are assumed to always succeed.
>
> Signed-off-by: Jorge Ramirez-Ortiz
> Reviewed-by:
On Sun, Feb 14, 2021 at 04:27:26PM +0100, Jorge Ramirez-Ortiz wrote:
> The Secure Channel Protocol 03 command sends control requests
> (enable/provision) to the TEE implementing the protocol between the
> processor and the secure element.
>
> Signed-off-by: Jorge Ramirez-Ortiz
> Reviewed-by: Sim
On Sun, Feb 14, 2021 at 04:27:28PM +0100, Jorge Ramirez-Ortiz wrote:
> From: Igor Opaniuk
>
> Add initial test coverage for SCP03 command.
>
> Signed-off-by: Igor Opaniuk
> Reviewed-by: Simon Glass
Applied to u-boot/next, thanks!
--
Tom
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On Sun, Feb 14, 2021 at 04:27:27PM +0100, Jorge Ramirez-Ortiz wrote:
> From: Igor Opaniuk
>
> Enable by default SCP_03/CMD_SCP03 for sandbox target.
>
> Signed-off-by: Igor Opaniuk
> Reviewed-by: Simon Glass
Applied to u-boot/next, thanks!
--
Tom
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On Mon, Mar 15, 2021 at 08:35:48AM +0100, Patrice CHOTARD wrote:
> Hi Tom
>
> Please pull the STM32 related patches for u-boot/master, v2021.07:
> u-boot-stm32-20210312
>
> CI status:
> https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/6732
>
>
> he following changes since comm
On Mon, Mar 15, 2021 at 02:39:10PM +0530, Lokesh Vutla wrote:
> Hi Tom,
> Please find the PR for master branch targeted for v2021.04-rc4 release.
> Details about the PR are updated in the tag message.
>
> Gitlab build report:
> https://source.denx.de/u-boot/custodians/u-boot-ti/-/pipelines
I keep getting a UnicodeDecodeError from one of the header files while
modifying the headers:
Traceback (most recent call last):
File "tools/moveconfig.py", line 1953, in
main()
File "tools/moveconfig.py", line 1927, in main
cleanup_headers(con
Skip the processing of *.aml and *.dat files while iterating through the
source in order to process header files.
Signed-off-by: Trevor Woerner
---
tools/moveconfig.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index dd92c00bb7..
Hey all,
It's release day, and here's v2021.04-rc4. Not a whole lot of change
since last time in master, and -next has been and is still open. I just
want to repeat a few things from -rc3:
- We've moved from "gitlab.denx.de" (and also "git.denx.de") to
"source.denx.de", please make sure to up
On 07.02.21 22:27, Simon Glass wrote:
> These were noticed when building sandbox on a Raspberry Pi 400, which uses
> 32-bit linux.
>
> To make this work, I enabled CONFIG_HOST_32BIT in 'make menuconfig'. It
> would be nice if that were automatic, since we have the logic already in
> arch/sandbox/co
On 3/1/21 6:08 PM, Biju Das wrote:
This patch series adds the required SoC/Board support to boot HopeRun
HiHope RZ/G2[HMN] boards. Board identification support for supporting
multidtb is derived from TF-A blob.
V8-->v9
* Use tf-a blob for identifying board type.
Applied all, thanks.
Integrate the Dockerfile from
https://source.denx.de/u-boot/gitlab-ci-runner.git as of
commit bc6130d572f1 ("Dockerfile: Remove high UID/GID") and introduce a
short rST on how to build the container.
Cc: Heinrich Schuchardt
Signed-off-by: Tom Rini
---
doc/build/docker.rst| 14 +++
doc/buil
Patch series for Engicam i.Core and MicroGEA SoM and it's
associated carrier board dts(i) support.
Changes for v2:
- add Linux dts commit ids in commit messages
- drop CONFIG_BOARD_EARLY_INIT_F
- order dts files in Makefile
- collect Patrice r-b
Any inputs?
Jagan.
Jagan Teki (9):
ARM: dts: stm
i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.
General features:
- STM32MP157A
- Up to 1GB DDR3L
- 4GB eMMC
- 10/100 Ethernet
- USB 2.0 Host/OTG
- I2S
- MIPI DSI to LVDS
- rest of STM32MP157A features
i.Core STM32MP1 needs to mount on top of Engicam baseboards
for creating com
Engicam i.Core STM32MP1 SODIMM SoM has mounted 1x4Gb DDR3
which has 32bits width 528000Khz frequency.
Add DDR configuration via dtsi.
Reviewed-by: Patrice Chotard
Signed-off-by: Jagan Teki
---
Changes for v2:
- collect Patrice r-b
.../stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi | 119 ++
SPI Load isn't mandatory for STM32 builds.
Let's imply instead of select it to get rid of build
issues for non-SPI defconfigs.
Reviewed-by: Patrice Chotard
Signed-off-by: Jagan Teki
---
Changes for v2:
- collect Patrice r-b
arch/arm/mach-stm32mp/Kconfig | 2 +-
1 file changed, 1 insertion(+),
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.
Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out
i.Core STM32MP1 is an EDIM
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.
Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector
i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam.
i.Core STM32MP1 needs to mount on top of this Carrie
MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.
General features:
- STM32MP157AAC
- Up to 1GB DDR3L-800
- 512MB Nand flash
- I2S
MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier
boards for creating complete platform solutions.
Linux dts commit details:
commit <0be81dfaeaf
Engicam MicroGEA STM32MP1 Micro SOM has mounted 1x4Gb DDR3
which has 16bits width 533Mhz frequency.
Add DDR configurations via dtsi.
Reviewed-by: Patrice Chotard
Signed-off-by: Jagan Teki
---
Changes for v2:
- collect Patrice r-b
...m32mp15-ddr3-microgea-1x4Gb-1066-binG.dtsi | 121 +++
MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.
Genaral features:
- Ethernet 10/100
- USB Type A
- Audio Out
- microSD
- LVDS panel connector
- Wifi/BT (option)
- UMTS LTE with sim connector (option)
MicroGEA STM32MP1 is a STM32MP157A based Micro
7" OF is a capacitive touch 7" Open Frame panel solutions with
- 7" AUO B101AW03 LVDS panel
- EDT, FT5526 Touch
MicroGEA STM32MP1 is a STM32MP157A based Micro SoM.
MicroDev 2.0 is a general purpose miniature carrier board with CAN,
LTE and LVDS panel interfaces.
MicroGEA STM32MP1 needs to mount
Patch series for Engicam i.Core MX8M Mini SOM and it's associated
carrier board dts(i) support.
patch 1-2: add imx8mm-u-boot.dtsi, header improvement code
patch 3: Engicam i.Core MX8M Mini SoM dts
patch 4-5: EDIMM2.2, C.TOUCH 2.0 Carrier boards
Changes for v2:
- add Linux commit sha1 in
/soc@0
aips1
aips2
aips3
clk
iomuxc
osc_24m
are common node enablements across imx8mm platform for
dm-spi, dm-pre-reloc stages.
Move them into common dtsi, imx8mm-u-boot.dtsi
Cc: Tim Harvey
Cc: Adam Ford
Cc: Peng Fan
Cc: Teresa Remmet
Cc: Igor Opaniuk
Signed-off-by: Jagan Teki
---
Changes
Move the redundant config item like SPL, memory-related
across all imx8mm config files in the common config header,
imx8mm-common.h
Verified the built files, seems almost the same as before.
Cc: Tim Harvey
Cc: Adam Ford
Cc: Peng Fan
Cc: Teresa Remmet
Cc: Igor Opaniuk
Signed-off-by: Jagan Tek
i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini
from Engicam.
General features:
- NXP i.MX8M Mini
- Up to 2GB LDDR4
- 8/16GB eMMC
- Gigabit Ethernet
- USB 2.0 Host/OTG
- PCIe Gen2 interface
- I2S
- MIPI DSI to LVDS
- rest of i.MX8M Mini features
i.Core MX8M Mini needs to mount on top of
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.
Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector
i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.
i.Core MX8M Mini needs to mount on top of this
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.
Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out
i.Core MX8M Mini is an EDI
Hi Heinrich,
On Mon, 15 Mar 2021 at 23:58, Heinrich Schuchardt wrote:
>
> On 3/15/21 6:11 AM, Simon Glass wrote:
> > This can crash if the EC has not yet been probed. Add a check to prevent
>
> What does 'This' relate to? There seems a sentence to missing from the
> commit message.
It refers to
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