>-Original Message-
>From: Ioana Ciornei
>Sent: Friday, May 15, 2020 12:27 PM
>To: Priyanka Jain ; u-boot@lists.denx.de
>Cc: Ioana Ciornei
>Subject: [PATCH v2 1/3] board: ls2080aqds: transition to DM_ETH
>
>In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2
>Ethernet d
On 16/05/2020 04:57, Seung-Woo Kim wrote:
> Hi Jaehoon,
>
> On 2020년 05월 15일 20:07, Jaehoon Chung wrote:
>> On 5/15/20 7:14 PM, Seung-Woo Kim wrote:
>>> On build with 32 bit, there is a warning for int-to-pointer-cast.
>>> Fix the int to pointer cast by using uintptr_t.
>>
>> Could you share in
Hi Simon,
-"Simon Glass" schrieb: -
> Betreff: Re: [PATCH v2 04/35] irq: Add a method to convert an interrupt to
> ACPI
>
> Hi Wolfgang,
>
> On Wed, 13 May 2020 at 07:01, Wolfgang Wallner
> wrote:
> >
> > Hi Simon,
> >
> > -"Simon Glass" schrieb: -
> > >Betreff: [PATCH v2 04/
Thanks for the review.
Will send v3 shortly.
On Mon, May 18, 2020 at 12:42 AM Beniamino Galvani wrote:
>
> On Sat, May 16, 2020 at 10:49:50PM +0300, Ramon Fried wrote:
> > [...]
> > index be9e6391d6..b85b44201f 100644
> > --- a/README
> > +++ b/README
> > @@ -3522,6 +3522,11 @@ List of environmen
Add support for RFC 7440: "TFTP Windowsize Option".
This optional feature allows the client and server
to negotiate a window size of consecutive blocks to send as an
alternative for replacing the single-block lockstep schema.
windowsize can be defined statically during compilation by
setting CONF
From: Ashok Reddy Soma
Remove below config options and convert them to macros. They have never
been configured to different values than default one. And also it makes
sense to reduce the config_whitelist.
CONFIG_SYS_ZYNQ_SPI_WAIT
CONFIG_SYS_ZYNQ_QSPI_WAIT
CONFIG_XILINX_SPI_IDLE_VAL
Signed-off-by
From: T Karthik Reddy
Fpga returns error value when fails, error status should be
printed in hex format.
Signed-off-by: T Karthik Reddy
Signed-off-by: Michal Simek
---
drivers/fpga/versalpl.c | 2 +-
drivers/fpga/zynqmppl.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
Am 17.05.20 um 18:24 schrieb Marek Vasut:
> Add Kconfig entries for the pcnet driver and convert MIPS malta
> to use those.
>
> Signed-off-by: Marek Vasut
> Cc: Daniel Schwierzeck
> Cc: Joe Hershberger
> ---
> configs/malta_defconfig | 1 +
> drivers/net/Kconfig | 6 ++
> include/co
> Subject: RE: [PATCH v2 1/3] board: ls2080aqds: transition to DM_ETH
>
> >-Original Message-
> >From: Ioana Ciornei
> >Sent: Friday, May 15, 2020 12:27 PM
> >To: Priyanka Jain ; u-boot@lists.denx.de
> >Cc: Ioana Ciornei
> >Subject: [PATCH v2 1/3] board: ls2080aqds: transition to DM_ET
On 5/18/20 11:18 AM, Daniel Schwierzeck wrote:
>
>
> Am 17.05.20 um 18:24 schrieb Marek Vasut:
>> Add Kconfig entries for the pcnet driver and convert MIPS malta
>> to use those.
>>
>> Signed-off-by: Marek Vasut
>> Cc: Daniel Schwierzeck
>> Cc: Joe Hershberger
>> ---
>> configs/malta_defconfi
Only load VBT if it's present in the u-boot.rom.
Signed-off-by: Bernhard Messerklinger
Reviewed-by: Simon Glass
Tested on coral:
Tested-by: Simon Glass
---
Changes in v4:
Fix comment alignment
Changes in v3: None
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 46 ++-
This patch series moves the configuration of FPS-S and FSP-M for Apollo
Lake based SoCs from the code to the devicetree.
In order to make the FSP configuration easy to extend and maintain new
binding structs for FSP-M and FSP-S are introduced.
These structs contain the information of which devicet
A the moment the FSP-S configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-S full configurable from devicetree by
adding binding properties for all FSP-S parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard M
A the moment the FSP-M configuration is a mix of hard coded values and
devicetree properties.
This patch makes FSP-M full configurable from devicetree by adding
binding properties for all FSP-M parameters.
Co-developed-by: Wolfgang Wallner
Signed-off-by: Wolfgang Wallner
Signed-off-by: Bernhard M
This patch set targets to add support for CONFIG_DM_ETH for the NXP
LS2080AQDS board.
The main focus is on changing the DTS based on the SERDES protocol used.
In order to accomplish this, the MULTI_DTB_FIT feature is employed and
the appropriate DTS is chosed on boot from a list of predefined file
In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2
Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH
is activated. Also, force the PCI devices to be enumerated at probe
time.
Signed-off-by: Ioana Ciornei
---
Changes in v3:
- fixed a build warning
board
Add support for selecting the appropriate DTS file depending on the
SERDES protocol used.
The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS
file specifically made for the current SERDES protocol.
This patch adds the necessary DPMAC nodes (DPMAC 1-8) for
protocol 42 (0x2A) on SD
Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the
LS2080AQDS board.
Signed-off-by: Ioana Ciornei
---
Changes in v3:
- none
configs/ls2088aqds_tfa_defconfig | 8
1 file changed, 8 insertions(+)
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_de
On 08.05.2020 04:56, Tiaki Rice wrote:
> This patch adds support for uart4 to the
> processor level device tree include file.
>
>
> Signed-off-by: Tiaki Rice
> Cc: Eugen Hristev
> ---
> Changes for v2:
> - Adjust commit message to comply with shortlog rules
> - Separate patch body into
On Fri, May 15, 2020 at 2:19 PM Pratyush Yadav wrote:
>
> On 15/05/20 01:14PM, Jagan Teki wrote:
> > On Fri, May 15, 2020 at 12:54 PM Pratyush Yadav wrote:
> > >
> > > Hi Jagan,
> > >
> > > On 14/05/20 05:41PM, Jagan Teki wrote:
> > > > env_flash is a global flash pointer, and the probe would
> >
On Sun, May 17, 2020 at 12:48:42PM +1000, Jonathan Gray wrote:
> On Sat, May 16, 2020 at 02:54:39PM -0400, Tom Rini wrote:
> > Add building the 'tools-only' target on macOS X 'Catalina'. Hopefully
> > this will catch changes to host tools that are incompatible on BSD style
> > environments.
> >
>
Provide a function for setting arbitrary virtual-physical MMU mapping
for the given region.
Signed-off-by: Marek Szyprowski
---
arch/arm/include/asm/mmu.h| 8
arch/arm/include/asm/system.h | 11 +++
arch/arm/lib/cache-cp15.c | 24 ++--
3 files change
Hi All,
This patchset add support for creating a mapping for the arbitrary
physical address at the given virtual address. This is needed to enable
support for XHCI USB controller on PCIe bridge on Raspberry Pi 4 board,
on which the USB controller's MMIO area 0x6 has to be remapped
somewher
Create a non-cacheable mapping for the 0x6 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
32bit mode, this region is mapped at 0xff80 CPU virtual address.
Signed-o
From: Seung-Woo Kim
On build with 32 bit, there is a warning for int-to-pointer-cast.
Fix the int to pointer cast by using uintptr_t.
Signed-off-by: Seung-Woo Kim
Signed-off-by: Marek Szyprowski
---
drivers/mmc/bcm2835_sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi Pratyush,
>-Original Message-
>From: U-Boot On Behalf Of Pratyush Yadav
>Sent: 30 March 2020 21:16
>To: Jagan Teki ; Vignesh Raghavendra
>
>Cc: Pratyush Yadav ; u-boot@lists.denx.de; Sekhar Nori
>
>Subject: [PATCH v3 10/17] mtd: spi-nor-core: Get command opcode extension
>type from BFP
On Mon, May 18, 2020 at 08:34:59AM +0200, Heinrich Schuchardt wrote:
> The following changes since commit 515f613253cf0a892c3a321770ab927fa3d925cf:
>
> Merge branch '2020-05-15-kconfig-migrations' (2020-05-15 21:44:46 -0400)
>
> are available in the Git repository at:
>
> https://gitlab.den
On Mon, May 18, 2020 at 01:42:32PM +0800, Bin Meng wrote:
> Hi Heiko,
>
> On Mon, May 18, 2020 at 12:28 PM Heiko Schocher wrote:
> >
> > Hello Tom,
> >
> > Am 09.04.2020 um 07:14 schrieb Heiko Schocher:
> > > Hello Tom,
> > >
> > > Am 19.02.2020 um 06:19 schrieb Heiko Schocher:
> > >> PowerPC tar
On Mon, May 18, 2020 at 11:55:11AM +0900, Masahiro Yamada wrote:
> Tom,
>
>
>
> On Thu, May 14, 2020 at 9:32 PM Tom Rini wrote:
> >
> > As part of re-syncing our Kconfig logic up to v4.19, we had missed
> > adding this new file that includes helper macros. To quote the upstream
> > commit e1cf
On 18/05/20 05:36PM, Jagan Teki wrote:
> On Fri, May 15, 2020 at 2:19 PM Pratyush Yadav wrote:
> >
> > On 15/05/20 01:14PM, Jagan Teki wrote:
> > > On Fri, May 15, 2020 at 12:54 PM Pratyush Yadav wrote:
> > > >
> > > > Hi Jagan,
> > > >
> > > > On 14/05/20 05:41PM, Jagan Teki wrote:
> > > > > env
On Thu, May 14, 2020 at 12:47 PM Michal Simek wrote:
>
> čt 14. 5. 2020 v 20:07 odesílatel Rob Herring napsal:
> >
> > On Thu, Apr 30, 2020 at 6:13 AM Michal Simek
> > wrote:
> > >
> > > On 29. 04. 20 16:55, Rob Herring wrote:
> > > > On Tue, Apr 28, 2020 at 8:51 AM Michal Simek
> > > > wrote
Am 18.05.20 um 11:54 schrieb Marek Vasut:
> On 5/18/20 11:18 AM, Daniel Schwierzeck wrote:
>>
>>
>> Am 17.05.20 um 18:24 schrieb Marek Vasut:
>>> Add Kconfig entries for the pcnet driver and convert MIPS malta
>>> to use those.
>>>
>>> Signed-off-by: Marek Vasut
>>> Cc: Daniel Schwierzeck
>>>
On 18. 05. 20 17:55, Rob Herring wrote:
> On Thu, May 14, 2020 at 12:47 PM Michal Simek wrote:
>>
>> čt 14. 5. 2020 v 20:07 odesílatel Rob Herring napsal:
>>>
>>> On Thu, Apr 30, 2020 at 6:13 AM Michal Simek
>>> wrote:
On 29. 04. 20 16:55, Rob Herring wrote:
> On Tue, Apr 28, 2020
From: Heiko Stuebner
Verifying FIT images obviously needs the rsa parts of crypto
support and while main uboot always compiles crypto support,
it's optional for SPL and we should thus select the necessary
option to not end up in compile errors like:
u-boot/lib/rsa/rsa-verify.c:328: undefined
From: Heiko Stuebner
While the SPL may want to do signature checking this won't be
the case for TPL in all cases, as TPL is mostly used when the
amound of initial memory is not enough for a full SPL.
So on a system where SPL uses DM but TPL does not we currently
end up with a TPL compile error o
From: Heiko Stuebner
Right now in multiple places there are only checks for the full
CONFIG_RSA_VERIFY_WITH_PKEY option, not split into main,spl,tpl variants.
This breaks when the rsa functions get enabled for SPL, for example to
verify u-boot proper from spl.
So fix this by using the existing
From: Heiko Stuebner
rsa-checksum needs support for hash functions or else will run into
compile errors like:
u-boot/lib/rsa/rsa-checksum.c:28: undefined reference to
`hash_progressive_lookup_algo'
So similar to the main FIT_SIGNATURE entry selects HASH,
select SPL_HASH_SUPPORT for SPL_FIT_SIGN
From: Heiko Stuebner
Right now in multiple places there are only checks for the full
CONFIG_RSA_VERIFY_WITH_PKEY option, not split into main,spl,tpl variants.
This breaks when the rsa functions get enabled for SPL, for example to
verify u-boot proper from spl.
So fix this by using the existing
> On 18.05.2020, at 18:06, Heiko Stuebner wrote:
>
> From: Heiko Stuebner
>
> While the SPL may want to do signature checking this won't be
> the case for TPL in all cases, as TPL is mostly used when the
> amound of initial memory is not enough for a full SPL.
nit: amound -> amount
> So on
On 5/8/20 11:54 AM, Jan Kiszka wrote:
> On 08.05.20 17:40, Andrew F. Davis wrote:
>> On 5/4/20 8:38 AM, Jan Kiszka wrote:
>>> From: Jan Kiszka
>>>
>>> Build the secured board dtbs (.dtb_HS) as part of the regular dtb build
>>> on CONFIG_TI_SECURE_DEVICE targets. This avoids rebuilding them,
>>> po
On 5/11/20 5:05 AM, Akashi Takahiro wrote:
> On Thu, Apr 30, 2020 at 11:06:23PM +0530, Sughosh Ganu wrote:
>> Change the semihosting file operation functions into external symbols
>> so that they can be called from outside the file. These functions
>> would be required to be called for implementing
On Mon, May 18, 2020 at 11:23:20AM -0400, Tom Rini wrote:
> On Mon, May 18, 2020 at 11:55:11AM +0900, Masahiro Yamada wrote:
> > Tom,
> >
> >
> >
> > On Thu, May 14, 2020 at 9:32 PM Tom Rini wrote:
> > >
> > > As part of re-syncing our Kconfig logic up to v4.19, we had missed
> > > adding this
On 4/30/20 7:36 PM, Sughosh Ganu wrote:
> Add a function to enable writing to a file. Currently, support is
> added for writing to a binary file. This would be used for
> implementing the firmware update functionality for the qemu arm64
> platform.
>
> Signed-off-by: Sughosh Ganu
> ---
> arch/arm
On 09/05/2020 11:04, Heinrich Schuchardt wrote:
On 5/6/20 5:04 PM, Grant Likely wrote:
On 05/05/2020 18:57, Heinrich Schuchardt wrote:
On 05.05.20 19:23, Grant Likely wrote:
On 05/05/2020 18:04, Heinrich Schuchardt wrote:
On 05.05.20 13:15, Grant Likely wrote:
On 01/05/2020 10:33, H
Hi Stefano,
Could you please check the status of this patchset and confirm if a v3
is required?
On 19/4/20 01:24, Walter Lozano wrote:
Hi Stefano,
I noticed that this series has state = Changes Requested, but not sure
what are the changes need.
Could you please clarify? There is a silly h
On 18.05.20 18:26, Andrew F. Davis wrote:
On 5/8/20 11:54 AM, Jan Kiszka wrote:
On 08.05.20 17:40, Andrew F. Davis wrote:
On 5/4/20 8:38 AM, Jan Kiszka wrote:
From: Jan Kiszka
Build the secured board dtbs (.dtb_HS) as part of the regular dtb build
on CONFIG_TI_SECURE_DEVICE targets. This avo
On Fri, May 15, 2020 at 03:40:41PM +0200, Remy Bohmer wrote:
> Hi,
>
> Regarding the Custodian workflow I have a general question: why do we
> follow a rebase flow for the custodian trees? If custodians merge master
> frequently into their own branches and merge that back on pull requests
> would
On 05/05/2020 00:14, Dan Murphy wrote:
Hello
The addition of the DP83867 driver to uboot was done in a generic way that
made it a bit difficult to bring in new PHY drivers. The difficulty came in the
config flags and the phy_init function. The change is to make the flags and
init for the DP
On Sat, May 16, 2020 at 05:54:43PM +0200, Michael Walle wrote:
> [Also adding Tom Rini as ARM maintainer]
>
> Am 2020-05-14 22:17, schrieb Alexander Graf:
> > On 14.05.20 20:46, Heinrich Schuchardt wrote:
> > > On 5/14/20 2:38 PM, Michael Walle wrote:
> > > > On some architectures, specifically th
Hi Pragnesh,
On 18/05/20 02:31PM, Pragnesh Patel wrote:
> Hi Pratyush,
>
> >-Original Message-
> >From: U-Boot On Behalf Of Pratyush Yadav
> >Sent: 30 March 2020 21:16
> >To: Jagan Teki ; Vignesh Raghavendra
> >
> >Cc: Pratyush Yadav ; u-boot@lists.denx.de; Sekhar Nori
> >
> >Subject: [P
Am May 18, 2020 6:30:09 PM UTC schrieb Tom Rini :
>On Sat, May 16, 2020 at 05:54:43PM +0200, Michael Walle wrote:
>> [Also adding Tom Rini as ARM maintainer]
>>
>> Am 2020-05-14 22:17, schrieb Alexander Graf:
>> > On 14.05.20 20:46, Heinrich Schuchardt wrote:
>> > > On 5/14/20 2:38 PM, Michael Wal
This is a side-port of commit 21c54b774744 ("kconfig: show compiler
version text in the top comment") from Linux:
"The kernel configuration phase is now tightly coupled with the compiler
in use. It will be nice to show the compiler information in Kconfig."
We have already had the required makefi
On Sun, May 17, 2020 at 01:49:30PM +0530, Rayagonda Kokatanur wrote:
> This is the second patch set series prepared on top of the
> first patch set ("add initial support for broadcom NS3 soc").
>
> This patch set will add following,
> -dt nodes and defconfig options for basic device like pinctrl,
On Mon, May 18, 2020 at 06:45:17PM +, Heinrich Schuchardt wrote:
> Am May 18, 2020 6:30:09 PM UTC schrieb Tom Rini :
> >On Sat, May 16, 2020 at 05:54:43PM +0200, Michael Walle wrote:
> >> [Also adding Tom Rini as ARM maintainer]
> >>
> >> Am 2020-05-14 22:17, schrieb Alexander Graf:
> >> > On
On Wed, 2020-05-13 at 16:10 -0400, Kurt Miller wrote:
> On Wed, 2020-05-13 at 22:58 +0300, Matwey V. Kornilov wrote:
> >
> > Thanks. Have you already checked it on gen2? I think I have gen2 board to
> > test.
> Yes, I have both gen3 and gen2 boards. gen2 continues to work
> with this patch as wel
Hi Marek,
On Mon, 18 May 2020 at 07:18, Marek Szyprowski wrote:
>
> Create a non-cacheable mapping for the 0x6 physical memory region,
> where MMIO registers for the PCIe XHCI controller are instantiated by the
> PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
> 32
Hi Anatolij and Heiko,
On Sun, May 17, 2020 at 8:19 AM Anatolij Gustschin wrote:
> I've tested i.MX8QXP based capricorn/giedi board (giedi_defconfig,
> imx8-giedi.dts)
> and it was not booting:
>
> U-Boot SPL 2020.07-rc2-00124-g515f613253 (May 16 2020 - 09:22:49 +0200)
> Trying to boot from MMC
I have a custom board that is similar to the i.MX6UL 14x14. One
difference is that it has an eMMC rather than a SD card. Most recently I
upgraded from u-boot 2019.07 to u-boot 2020.01 and now u-boot cannot
detect the eMMC anymore.
For the 2019.07 version I did use CONFIG_FSL_ESDHC=y without
CONFIG
On Tue, May 19, 2020 at 1:55 AM Tom Rini wrote:
>
> On Mon, May 18, 2020 at 11:23:20AM -0400, Tom Rini wrote:
> > On Mon, May 18, 2020 at 11:55:11AM +0900, Masahiro Yamada wrote:
> > > Tom,
> > >
> > >
> > >
> > > On Thu, May 14, 2020 at 9:32 PM Tom Rini wrote:
> > > >
> > > > As part of re-synci
When eSDHC operates at 3.3v, damage can accumulate in an internal
level shifter at a higher than expected rate. The faster the interface
runs, the more damage accumulates. This issue now is found on LX2160A
eSDHC1 for only SD card.
The hardware workaround is recommended to use an on-board level sh
No need to poll register for card inserted status.
Signed-off-by: Yangbo Lu
---
Changes for v2:
- Updated copyright.
---
drivers/mmc/fsl_esdhc.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 386781d..0
> Subject: [v2, 1/2] mmc: fsl_esdhc: read register once for card inserted status
>
> No need to poll register for card inserted status.
>
> Signed-off-by: Yangbo Lu
Acked-by: Peng Fan
> Subject: [v2, 2/2] mmc: fsl_esdhc: workaround for hardware 3.3v IO reliability
> issue
>
> When eSDHC operates at 3.3v, damage can accumulate in an internal level
> shifter at a higher than expected rate. The faster the interface runs, the
> more
> damage accumulates. This issue now is found on
> Subject: [PATCH] mmc: retry CMD1 in mmc_send_op_cond() until the eMMC
> is ready
>
> From: Haibo Chen
>
> According to eMMC specification v5.1 section 6.4.3, we should issue
> CMD1 repeatedly in the idle state until the eMMC is ready even if
> mmc_send_op_cond() send CMD1 with argument = 0. Ot
Hello Tom, Bin,
Am 18.05.2020 um 17:17 schrieb Tom Rini:
On Mon, May 18, 2020 at 01:42:32PM +0800, Bin Meng wrote:
Hi Heiko,
On Mon, May 18, 2020 at 12:28 PM Heiko Schocher wrote:
Hello Tom,
Am 09.04.2020 um 07:14 schrieb Heiko Schocher:
Hello Tom,
Am 19.02.2020 um 06:19 schrieb Heiko Sc
Hello Fabio, Anatolij,
Am 19.05.2020 um 01:32 schrieb Fabio Estevam:
Hi Anatolij and Heiko,
On Sun, May 17, 2020 at 8:19 AM Anatolij Gustschin wrote:
I've tested i.MX8QXP based capricorn/giedi board (giedi_defconfig,
imx8-giedi.dts)
and it was not booting:
U-Boot SPL 2020.07-rc2-00124-g515
I solved the problem with u-boot not recognizing the eMMC. The device
tree is working now for u-boot.
However, i.MX6 is using SPL which is loaded into OCRAM. If I flash SPL
and u-boot to a boot partition on the eMMC the boot ROM loads SPL just
fine but then SPL cannot load u-boot from eMMC:
Tryin
RFC2348, RFC2349:
- Option string is case in-sensitive.
- Client must generate ERR pkt in case option value mismatch in server OACK
- Fix debug print for options
Signed-off-by: Ravik Hasija
---
net/tftp.c | 59 +++---
1 file changed, 52 insertions
On Mon, May 18, 2020 at 6:33 PM Bernhard Messerklinger
wrote:
>
> This patch series moves the configuration of FPS-S and FSP-M for Apollo
> Lake based SoCs from the code to the devicetree.
>
> In order to make the FSP configuration easy to extend and maintain new
> binding structs for FSP-M and FS
Hello Alex,
Am 14.05.2020 um 22:11 schrieb Alex Nemirovsky:
From: Arthur Li
Add I2C controller support for Cortina Access CA SoCs
Signed-off-by: Arthur Li
Signed-off-by: Alex Nemirovsky
CC: Heiko Schocher
CA_I2C: DT binding for I2C controller
DT binding document for Cortina I2C drive
Hello Alex,
Am 14.05.2020 um 22:11 schrieb Alex Nemirovsky:
Add I2C board support for Cortina Access Presidio Engineering Board
Signed-off-by: Alex Nemirovsky
CC: Heiko Schocher
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in
Hello Stefan,
Am 14.05.2020 um 09:23 schrieb Stefan Roese:
From: Suneel Garapati
Add support for I2C controllers found on Octeon II/III and Octeon TX
TX2 SoC platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Suneel Garapati
Signed-off-by: Stefan Roese
Cc: Heiko Schocher
Cc: Simon Gl
Hi Jan,
On 18/05/20 11:27 am, Jan Kiszka wrote:
> From: Jan Kiszka
>
> Add support for enabling dcache already in SPL. It accelerates the boot
> and resolves the risk to run into unaligned 64-bit accesses.
>
> Based on original patch by Lokesh Vulta.
>
> Signed-off-by: Jan Kiszka
Thanks for
On 19.05.20 08:18, Lokesh Vutla wrote:
Hi Jan,
On 18/05/20 11:27 am, Jan Kiszka wrote:
From: Jan Kiszka
Add support for enabling dcache already in SPL. It accelerates the boot
and resolves the risk to run into unaligned 64-bit accesses.
Based on original patch by Lokesh Vulta.
Signed-off-by
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