Hi Jerome / Neil,
[...]
>
> I'm not quite sure I get what I should understand from this log.
>
> I can comment on the original patch though.
>
> I think you should keep the phase settings aligned with Linux.
>
Thanks for this inputs.
> A) Among the exchange I had with amlogic, I got that there sh
When U-Boot is not the first-stage bootloader the FSP-S init must be
skipped. Update it to add a check.
Signed-off-by: Simon Glass
---
arch/x86/cpu/apollolake/fsp_s.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 98
When U-Boot is no the first-stage bootloader much of this code is not
needed and can break booting. Add checks for this to the FSP code.
Rather than checking for the amount of available SDRAM, just use 1GB in
this situation, which should be safe. Using 2GB may run into a memory
hole on some SoCs.
When U-Boot is not the first-stage bootloader we don't want to init
devices early during boot. Add a check to avoid this.
Signed-off-by: Simon Glass
---
common/board_r.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/common/board_r.c b/common/board_r.c
index e711de64b5..4e0dfac4fc 10064
This little series adds a few checks into the code to allow better
operation when booting a build from a previous-state loader such as
coreboot.
At present we have a 'coreboot' target, but sometimes it is useful to boot
a bare-metal target, such as coral, from coreboot. That allows comparison
of o
When U-Boot is not the first-stage bootloader the interrupt and cache init
must be skipped, as well as init for various peripherals. Update the code
to add checks for this.
Signed-off-by: Simon Glass
---
arch/x86/cpu/cpu.c| 4 +++-
arch/x86/cpu/i386/interrupt.c | 3 +++
arch/x86/lib
When U-Boot is not the first-stage bootloader we don't want to
re-configure the PCI devices, since this has already been done. Add a
check to avoid this.
Signed-off-by: Simon Glass
---
drivers/pci/pci-uclass.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/p
If a different input clock is required then the correct way to do this is
with a clock driver. Don't allow boards to override IC_CLK.
Signed-off-by: Simon Glass
---
drivers/i2c/designware_i2c.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/desig
This series updates the Designware I2C driver to support reading its
timing from the device tree and handling it in units of nanoseconds
instead of clock cycles.
A new function converts from nanoseconds to the units used by the I2C
controller and makes sure that the requested bus speed is not exce
Some versions of this peripherals previde more control of the bus
behaviour. Add definitions for these registers.
Signed-off-by: Simon Glass
---
drivers/i2c/designware_i2c.h | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/designware_i2c.h b/drivers/
We use struct clk here so really should include this header file to avoid
build errors. Also switch the order of clk.h in the C file to match the
required code style.
Signed-off-by: Simon Glass
---
drivers/i2c/designware_i2c.c | 2 +-
drivers/i2c/designware_i2c.h | 1 +
2 files changed, 2 inser
Group these #defines into an enum to make it easier to understand the
relationship between them.
Signed-off-by: Simon Glass
---
drivers/i2c/designware_i2c.c | 2 +-
drivers/i2c/designware_i2c.h | 10 +++---
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/i2c/designwa
Some SoCs support a higher speed than what is currently called 'max' in
this driver. Rename it to 'high' speed, which is the official name of the
3.4MHz speed.
Signed-off-by: Simon Glass
---
drivers/i2c/designware_i2c.c | 10 +-
drivers/i2c/designware_i2c.h | 8
2 files change
At present the driver uses an approximation for the bus clock, e.g. 166MHz
instead of 166 2/3 MHz.
This can result in small errors in the resulting I2C speed, perhaps 0.5%
or so.
Adjust the existing code to start from the accurate figure, even if later
rounding reduces this accuracy.
Update the
Create a struct to hold the three timing parameters. This will make it
easier to move these calculations into a separate function in a later
patch.
Signed-off-by: Simon Glass
---
drivers/i2c/designware_i2c.c | 82
1 file changed, 55 insertions(+), 27 deletio
Bring in this file from Linux v5.4.
Signed-off-by: Simon Glass
---
.../i2c/i2c-designware.txt| 73 +++
1 file changed, 73 insertions(+)
create mode 100644 doc/device-tree-bindings/i2c/i2c-designware.txt
diff --git a/doc/device-tree-bindings/i2c/i2c-designwa
Instead of passing this parameter into __dw_i2c_set_bus_speed(), pass in
the driver's private data, from which the function can obtain that
information. This allows the function to have access to the full state of
the driver.
Signed-off-by: Simon Glass
---
drivers/i2c/designware_i2c.c | 14
The i2c controller defines a few timing properties. Read these in and
store them for use by the driver.
Signed-off-by: Simon Glass
---
drivers/i2c/designware_i2c.c | 8 ++--
drivers/i2c/designware_i2c.h | 15 +++
drivers/i2c/designware_i2c_pci.c | 2 +-
3 files changed
At present the driver can end up with timing parameters which are slightly
faster than those expected. It is possible to optimise the parameters to
get the best possible result.
Create a new function to handle the timing calculation. This uses a table
of defaults for each speed mode rather than wr
Some versions of this peripheral include a spike-suppression phase of the
bus. Add support for this.
Signed-off-by: Simon Glass
---
drivers/i2c/designware_i2c.c | 10 +-
drivers/i2c/designware_i2c.h | 2 ++
drivers/i2c/designware_i2c_pci.c | 2 ++
3 files changed, 13 insertion
On Sat, Dec 21, 2019 at 6:13 PM Simon Glass wrote:
>
> This little series adds a few checks into the code to allow better
> operation when booting a build from a previous-state loader such as
> coreboot.
>
> At present we have a 'coreboot' target, but sometimes it is useful to boot
> a bare-metal
The omap3_beagle NAND ECC scheme was changed in 4b37928d357 for unknown
reasons, leading to uncorrectible ecc errors. This commit changes it
back to what it was before.
Signed-off-by: Patrik Dahlström
---
include/configs/omap3_beagle.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
If baud_divisor is not set (i.e. == -1), we should use the baud divisor
already in use for flushing the xmit register. If we don't flush the
xmit register, then SPL will hang.
Signed-off-by: Patrik Dahlström
---
drivers/serial/ns16550.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/
This series adds a driver for the Cr50 security chip and enables it on
coral. This supports the 'tpm' command.
In order to make this work a few other changes are included:
- Additional UCLASS_IRQ operations to support requesting and reading
interrupts, using the device tree
- A driver for ACPI g
Hi Andy,
On Sat, 21 Dec 2019 at 10:00, Andy Shevchenko wrote:
>
> On Sat, Dec 21, 2019 at 6:13 PM Simon Glass wrote:
> >
> > This little series adds a few checks into the code to allow better
> > operation when booting a build from a previous-state loader such as
> > coreboot.
> >
> > At present
Enable the Intel clock driver and modify coral's device tree to use it.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/x86/cpu/apollolake/Kconfig | 3 +++
arch/x86/dts/chromebook_coral.dts | 6 ++
2 files changed, 9 insertions(+)
diff --git a/arch/x86/cpu/apollolake/Kconfig b/a
These are actually working correctly, so update the status.
Signed-off-by: Simon Glass
---
Changes in v2: None
doc/board/google/chromebook_coral.rst | 2 --
1 file changed, 2 deletions(-)
diff --git a/doc/board/google/chromebook_coral.rst
b/doc/board/google/chromebook_coral.rst
index 515fd06
So far we have avoided adding a clock driver for Intel devices. But the
Designware I2C driver needs a different clock (133MHz) on Intel devices
than on others (166MHz). Add a simple driver that provides this
information.
This driver can be expanded later as needed.
Signed-off-by: Simon Glass
---
This config is not actually used here and in U-Boot it seems better to set
this using the device tree for each individual controller. The monolithic
config of the FSP-S is only necessary if the FSP is actually configuring
something, but here it is not.
The FSP-S does enable/disable the various I2C
Add an IRQ type to each driver and use irq_first_device_type() to find
and probe the correct one.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/x86/cpu/apollolake/fsp_s.c | 4 ++--
arch/x86/cpu/apollolake/itss.c | 2 +-
arch/x86/cpu/i386/interrupt.c | 3 ++-
arch/x86/cpu/irq.c
There can be different types of interrupt controllers in a system and some
drivers may need to distinguish between these. In general this can be
handled using the device tree by adding the interrupt information to
device nodes.
However on x86 devices we have interrupt controllers which are not tie
At present driver model supports the IRQ uclass but there is no way to
request a particular interrupt for a driver.
Add a mechanism, similar to clock and reset, to read the interrupts
required by a device from the device tree and to request those interrupts.
U-Boot itself does not have interrupt-
Allow this driver to be used in TPL by setting up the interrupt type
correctly.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/x86/cpu/apollolake/itss.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/x86/cpu/apollolake/itss.c b/arch/x86/cpu/apollolake/itss.c
inde
ACPI GPEs are used to signal interrupts from peripherals that are accessed
via ACPI. In U-Boot these are modelled as interrupts using a separate
interrupt controller. Configuration is via the device tree.
Add a simple driver for this.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/x8
Enable TPM2 so that we can use cr50.
Signed-off-by: Simon Glass
---
Changes in v2:
- Update the commit message
- Add new patches to handle requesting interrupts and interrupt state
configs/chromebook_coral_defconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/configs/
Add definitions for access and status.
Need to drop the mixed case.
Signed-off-by: Simon Glass
---
Changes in v2: None
include/tpm-v2.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/include/tpm-v2.h b/include/tpm-v2.h
index ae00803f6d..d53d2e4023 100644
Add nodes to the device tree for Cr50 and other available I2C ports. Also
enable the ACPI interrupt driver.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/x86/cpu/apollolake/Kconfig | 1 +
arch/x86/dts/chromebook_coral.dts | 87 +++
2 files changed, 88 i
H1 is a Google security chip present in recent Chromebooks, Pixel phones
and other devices. Cr50 is the name of the software that runs on H1 in
Chromebooks.
This chip is used to handle TPM-like functionality and also has quite a
few additional features.
Add a driver for this.
Signed-off-by: Simo
The following changes since commit 643366bcd5e32878a951e39b8b553b794695b026:
Merge tag 'u-boot-stm32-20191218' of
https://gitlab.denx.de/u-boot/custodians/u-boot-stm (2019-12-18 08:25:49
-0500)
are available in the Git repository at:
git://git.denx.de/u-boot-usb.git master
for you to fetch
On Sat, Dec 21, 2019 at 05:18:22PM +0100, Patrik Dahlström wrote:
> The omap3_beagle NAND ECC scheme was changed in 4b37928d357 for unknown
> reasons, leading to uncorrectible ecc errors. This commit changes it
> back to what it was before.
>
Hello Patrick,
Is there a setup/test that you are usi
On a VT100 terminal [2J should be enough to both clear the whole
screen and set the cursor to position (1, 1). But the Linux console does
not behave like this. So send an extra [H. For reference see the
console_codes(4) man page.
Add a function description.
Signed-off-by: Heinrich Schuchardt
---
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