When enabling back-to-bootrom, the bootrom would continue to load the
second level boot-loader. And currently we are packing it by appending
the generated image manually (with a predefined max size):
./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \
firefly-rk3288/spl/u-boot-spl-dtb.bin o
>-Original Message-
>From: Biwen Li
>Sent: Thursday, December 5, 2019 11:41 AM
>To: Jagdish Gediya ; Priyanka Jain
>; h...@denx.de; ja...@amarulasolutions.com;
>aford...@gmail.com; Alison Wang ;
>bhaskar.upadh...@nxp.com; feng.l...@nxp.com; jh80.ch...@samsung.com;
>Pramod Kumar ; Rajesh
Since, commit 62f9b6544728 ("common: Move older CPU functions to their own
header")
cache ops functions are declared in a separate header. Include the same
to avoid build warnings.
Signed-off-by: Vignesh Raghavendra
---
drivers/usb/cdns3/ep0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a
Support packing optional second level boot-loader:
$ ./tools/mkimage -n rk3399 -T rksd -d \
rk3399_ddr_800MHz_v1.24.bin:rk3399_miniloader_v1.19.bin out -v
Adding Image rk3399_ddr_800MHz_v1.24.bin
Size 116492(pad to 116736)
Adding Image rk3399_miniloader_v1.19.bin
Size 88060(pad to 88064)
Image T
On Thu, Oct 03, 2019 at 07:50:12PM +0200, Miquel Raynal wrote:
> UBI must be enabled when the environment is in UBI.
>
> Signed-off-by: Miquel Raynal
> Reviewed-by: Boris Brezillon
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
Add an entry for allowing clock enablement for the random number
generator peripheral, RNG1.
Signed-off-by: Sughosh Ganu
Reviewed-by: Patrice Chotard
---
drivers/clk/clk_stm32mp1.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index
Add a sandbox driver for random number generation. Mostly aimed at
providing a unit test for rng uclass.
Signed-off-by: Sughosh Ganu
Reviewed-by: Patrice Chotard
---
arch/sandbox/dts/test.dts | 4
drivers/rng/Kconfig | 7 +++
drivers/rng/Makefile | 1 +
drivers/rng/sandbo
Enable support for random number generator on sandbox configs. This is
aimed primarily at adding unit test support for rng uclass.
Signed-off-by: Sughosh Ganu
Reviewed-by: Patrice Chotard
---
configs/sandbox64_defconfig | 2 ++
configs/sandbox_defconfig | 2 ++
2 files changed, 4 insertions(+
Add a unit test for testing the rng uclass functionality using the
sandbox rng driver.
Signed-off-by: Sughosh Ganu
Reviewed-by: Patrice Chotard
---
test/dm/Makefile | 1 +
test/dm/rng.c| 26 ++
2 files changed, 27 insertions(+)
create mode 100644 test/dm/rng.c
dif
On Thu, Oct 03, 2019 at 07:50:20PM +0200, Miquel Raynal wrote:
> Enabling TFABOOT configuration will compile-in a call to nand_read in
> the boot sequence. Handle the situation by also selecting officially
> the raw NAND core in this case.
>
> Signed-off-by: Miquel Raynal
Applied to u-boot/mast
Enable support for the rng device on the stm32mp15 configs.
Signed-off-by: Sughosh Ganu
Reviewed-by: Patrice Chotard
---
configs/stm32mp15_basic_defconfig | 2 ++
configs/stm32mp15_optee_defconfig | 2 ++
configs/stm32mp15_trusted_defconfig | 2 ++
3 files changed, 6 insertions(+)
diff --g
Add a uclass for reading a random number seed from a random number
generator device.
Signed-off-by: Sughosh Ganu
Reviewed-by: Patrice Chotard
---
Changes since V1:
* Add a SPDX header in rng.h
* Change the UCLASS_DRIVER name from hwrng to rng, to be consistent
with the rest of the naming conv
Follow i.MX, Sunxi, RISC-V and Rockchip to generate u-boot.itb which
includes U-Boot proper, ATF and DTBs in FIT format. ZynqMP supports FIT for
quite a long time but with using out of tree solution. The patch is filling
this gap.
Tested on zcu102, zcu104 and zcu100/Ultra96.
zcu100/Ultra96 v2.2 A
Add documentation about packing optional second level boot-loader with
mkimage tool.
Signed-off-by: Jeffy Chen
---
doc/README.rockchip | 11 +++
1 file changed, 11 insertions(+)
diff --git a/doc/README.rockchip b/doc/README.rockchip
index 67c14006a3..39dc9c5e9f 100644
--- a/doc/README.
Add a driver for the rng device found on stm32mp1 platforms. The
driver provides a routine for reading the random number seed from the
hardware device.
Signed-off-by: Sughosh Ganu
---
Changes since V1:
* Handle review comment from Patrice Chotard to remove the 'inited'
member
drivers/rng/Kco
>-Original Message-
>From: Biwen Li
>Sent: Thursday, December 5, 2019 11:40 AM
>To: Jagdish Gediya ; Priyanka Jain
>; h...@denx.de; ja...@amarulasolutions.com;
>aford...@gmail.com; Alison Wang ;
>bhaskar.upadh...@nxp.com; feng.l...@nxp.com; jh80.ch...@samsung.com;
>Pramod Kumar ; Rajesh
Update the SPL_STACK_R_MALLOC_SIMPLE_LEN which also including space for
STACK and the size may not enough when loding FIT image in SPL.
If the size is not enough, you can see log like this when loding FIT:
U-Boot TPL 2020.01-rc3-00082-g4b19b89ca4-dirty (Dec 05 2019 - 11:52:53)
Trying to boot from
The OPTEE will use the ram start at 0x840 which make the DRAM be two
banks.
Signed-off-by: Kever Yang
---
configs/evb-rk3288_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 685120cd78..9391328bce
Add support for Octal flash devices. Octal flash devices use 8 IO lines
for data transfer. Currently only 1-1-8 Octal Read mode is supported.
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi/sf_internal.h | 3 ++-
drivers/mtd/spi/spi-nor-core.c | 20 +++-
drivers/spi/spi-
This series adds Octal mode support for Micron's mt35x flash.
Also adds Octal mode support for Cadance OSPI/QSPI controller.
Currently only 1-1-8 mode is supported.
Vignesh Raghavendra (3):
mtd: spi-nor-core: Add octal mode support
spi: cadence-qspi: Add support for Cadence Octal SPI controlle
Cadence OSPI is similar to QSPI IP except that it supports Octal IO
(8 IO lines) flashes. Add support for Cadence OSPI IP with existing
driver using new compatible
Signed-off-by: Vignesh Raghavendra
---
drivers/spi/cadence_qspi.c | 1 +
drivers/spi/cadence_qspi_apb.c | 8 ++--
2 files ch
TI's AM654 SoC has a Cadence OSPI IP. Add a new compatible string for
the same.
Signed-off-by: Vignesh Raghavendra
---
drivers/spi/cadence_qspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 6374d3976a4a..f8b69406d4b9 100644
--
út 3. 12. 2019 v 20:56 odesílatel Heinrich Schuchardt
napsal:
>
> On 12/2/19 3:21 PM, Michal Simek wrote:
> > On 29. 11. 19 19:23, Heinrich Schuchardt wrote:
> >> On 11/29/19 11:16 AM, Michal Simek wrote:
> >>> Hi,
> >>>
> >>> I tried to boot latest debian and fedora rootfs via distro boot and
> >
Instead of hardcode the base address, we can get them from the build
output, eg. get the SYS_TEXT_BASE from .config and get optee base from
DRAM_BASE.
We can use this script for SoCs with DRAM base not from 0x6000(rk3229
and many other 32bit Rockchip SoCs), eg. rk3288 DRAM base is 0.
Signed-of
Upstream kernel and rockchip kernel has default enable PSCI which needs
OPTEE in trust word, enable OPTEE support for evb by default and SPL_FIT
option to pack OPTEE with U-Boot proper.
Signed-off-by: Kever Yang
---
configs/evb-rk3288_defconfig | 5 +
1 file changed, 5 insertions(+)
diff -
On 12/5/19 9:42 AM, Sughosh Ganu wrote:
> Add a driver for the rng device found on stm32mp1 platforms. The
> driver provides a routine for reading the random number seed from the
> hardware device.
>
> Signed-off-by: Sughosh Ganu
> ---
>
> Changes since V1:
> * Handle review comment from Patrice C
On Thu, Dec 05, 2019 at 04:17:38AM +0200, Aleksandr Bulyshchenko wrote:
>Hello Sam,
>I'd like to add my 5 cents regarding separating dtimg start|size into 3
>subcommands
>
> dtimg start index [varname]
> dtimg start id [varname]
> dtimg start rev [varname]
>
>While I don'
Add documentation about packing optional second level boot-loader with
mkimage tool.
Signed-off-by: Jeffy Chen
---
Changes in v2: None
doc/README.rockchip | 11 +++
1 file changed, 11 insertions(+)
diff --git a/doc/README.rockchip b/doc/README.rockchip
index 67c14006a3..39dc9c5e9f 100
When enabling back-to-bootrom, the bootrom would continue to load the
second level boot-loader. And currently we are packing it by appending
the generated image manually (with a predefined max size):
./firefly-rk3288/tools/mkimage -n rk3288 -T rksd -d \
firefly-rk3288/spl/u-boot-spl-dtb.bin o
Support packing optional second level boot-loader:
$ ./tools/mkimage -n rk3399 -T rksd -d \
rk3399_ddr_800MHz_v1.24.bin:rk3399_miniloader_v1.19.bin out -v
Adding Image rk3399_ddr_800MHz_v1.24.bin
Size 116492(pad to 116736)
Adding Image rk3399_miniloader_v1.19.bin
Size 88060(pad to 88064)
Image T
Hi Lukasz,
On Thu, Dec 5, 2019 at 12:46 AM Lukasz Majewski wrote:
>
> Hi Igor,
>
> > From: Igor Opaniuk
> >
> > Add universal update_uboot wrapper that helps to update
> > U-Boot image on internal storage.
> >
> > > tftpboot ${loadaddr} ${board_name}/u-boot.img
> > > run update_uboot
> > > tftpb
Good Evening,
I am trying to get TPL/SPL working on the rk3328-firefly ddr4 4gb board.
I've pulled the ddr4 dtsi from the rockchip u-boot repository [0].
Unfortunately I cannot get the ddr4 to detect correctly.
With the u-boot tpl, I get the following:
U-Boot TPL 2020.01-rc3-00072-g1a1bea82b2-di
The rc4 encoding should cover spl header as well, and the file_size
contains spl header too.
Signed-off-by: Jeffy Chen
---
Changes in v2: None
tools/rkimage.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/rkimage.c b/tools/rkimage.c
index ae50de55c9..1c5540b1c3 1006
Hello Sam,
I'd like to add my 5 cents regarding separating dtimg start|size into 3
subcommands
> dtimg start index [varname]
> dtimg start id [varname]
> dtimg start rev [varname]
>
> While I don't see real usecases for combining index with id or rev (if
someone applies metainformation to d
On 12/5/19 11:21 AM, Michal Simek wrote:
I have separate partitions:
/boot of type 83 (Linux, ext2) and marked as bootable and with boot.scr
on it.
/boot/efi of type ef (EFI, vfat) and not marked as bootable
The sequence on the block device does not matter.
When booting via iSCSI with iPXE I p
From: Suresh Channappa
Add bnxt L2 driver support.
This driver is used by several Broadcom iProc platforms.
Signed-off-by: Suresh Channappa
Signed-off-by: Vladimir Olovyannikov
---
drivers/net/Kconfig |1 +
drivers/net/Makefile|1 +
drivers/net/bnxt/Kconfig|8 +
Add a random number generator(rng) uclass to facilitate adding drivers
for rng devices. I plan to add an implementation of the
EFI_RNG_PROTOCOL, which would get the random number from the rng
uclass -- the protocol would be used by the efi stub for getting a
random number for the kaslr feature.
Th
On 12/5/19 8:59 AM, Vignesh Raghavendra wrote:
> Since, commit 62f9b6544728 ("common: Move older CPU functions to their own
> header")
> cache ops functions are declared in a separate header. Include the same
> to avoid build warnings.
Applied, thanks.
Hi Aleksandr,
On Thu, Dec 5, 2019 at 4:17 AM Aleksandr Bulyshchenko
wrote:
>
> Hello Sam,
>
> I'd like to add my 5 cents regarding separating dtimg start|size into 3
> subcommands
>>
>> dtimg start index [varname]
>> dtimg start id [varname]
>> dtimg start rev [varname]
>
> While I don't s
On Thu, Dec 05, 2019 at 09:46:57AM +0100, Michal Simek wrote:
> Follow i.MX, Sunxi, RISC-V and Rockchip to generate u-boot.itb which
> includes U-Boot proper, ATF and DTBs in FIT format. ZynqMP supports FIT for
> quite a long time but with using out of tree solution. The patch is filling
> this gap
On Tue, Dec 03, 2019 at 08:51:09PM +0100, Heinrich Schuchardt wrote:
> On 12/2/19 3:21 PM, Michal Simek wrote:
> > On 29. 11. 19 19:23, Heinrich Schuchardt wrote:
> >> On 11/29/19 11:16 AM, Michal Simek wrote:
> >>> Hi,
> >>>
> >>> I tried to boot latest debian and fedora rootfs via distro boot and
On Mon, Aug 26, 2019 at 05:54:59AM -0700, Niv Shetrit wrote:
> Signed-off-by: Niv Shetrit
Sorry for taking so long to get back to this. A few problems. And
re-ordering the diff to make explanation clearer:
> ---
> common/cli_hush.c | 73 ---
> 1 fi
On 2019/12/5 下午3:48, Jeffy Chen wrote:
Support packing optional second level boot-loader:
$ ./tools/mkimage -n rk3399 -T rksd -d \
rk3399_ddr_800MHz_v1.24.bin:rk3399_miniloader_v1.19.bin out -v
Adding Image rk3399_ddr_800MHz_v1.24.bin
Size 116492(pad to 116736)
Adding Image rk3399_miniloade
On 2019/12/3 下午1:24, Ben Wolsieffer wrote:
This enables reading of the cpuid and a static MAC address.
Signed-off-by: Ben Wolsieffer
Reviewed-by: Kever Yang
Thanks,
- Kever
---
configs/rock64-rk3328_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/rock64-rk3328_
On 2019/12/3 下午1:40, Ben Wolsieffer wrote:
Recent versions of the Linux kernel with many options enabled have
grown large enough to overwrite the beginning of the initrd. For
example, the kernel I use on my Rock64 and RockPro64 is 34.1 MiB,
while only 31.5 MiB are available between kernel_addr_
On 2019/12/3 下午5:49, David Wu wrote:
This PWM driver can be used to support pwm functions
for on all Rockchip Socs.
The previous chips than RK3288 did not support polarity,
and register layout was different from the RK3288 PWM.
The RK3288 keep the current functions.
RK3308 and the chips afte
On 2019/12/3 下午7:02, David Wu wrote:
When we want to use plus pinctrl feature, we need to enable
them at spl.
Signed-off-by: David Wu
---
Change in v2:
- Fix GPIO3B2_SEL_SRC_CTRL_SEL_PLUS
arch/arm/mach-rockchip/rk3308/rk3308.c | 37 ++
Reviewed-by: Kever Yang
T
On 2019/12/3 下午7:26, David Wu wrote:
An iomux register contains 8 pins, each of which is represented
by 2 bits, but the register offset is 0x8.
For example, GRF_GPIO0A_IOMUX offset is 0x0, but GRF_GPIO0B_IOMUX
offset is 0x8, the offset 0x4 is reserved.
So add a type IOMUX_8WIDTH_2BIT to calcu
On 2019/12/5 下午6:58, Jeffy Chen wrote:
Support packing optional second level boot-loader:
$ ./tools/mkimage -n rk3399 -T rksd -d \
rk3399_ddr_800MHz_v1.24.bin:rk3399_miniloader_v1.19.bin out -v
Adding Image rk3399_ddr_800MHz_v1.24.bin
Size 116492(pad to 116736)
Adding Image rk3399_miniloade
On 2019/11/26 上午9:39, David Wu wrote:
The Firefly ROC_RK3308_CC use ref_clock of input mode,
and rmii pins of m1 group.
Signed-off-by: David Wu
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3308-roc-cc.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/a
On 2019/11/26 上午9:39, David Wu wrote:
The rk3308 only support RMII mode, and if it is output clock
mode, better to use ref_clk pin with drive strength 12ma.
Signed-off-by: David Wu
Reviewed-by: Kever Yang
Thanks,
- Kever
---
arch/arm/dts/rk3308.dtsi | 22 ++
1 file
On Tue, Nov 26, 2019 at 09:51:20AM +0900, AKASHI Takahiro wrote:
> Pytest for UEFI secure boot will use several host commands.
> In paricular, Test setup relies on efitools, whose version must be v1.5.2
> or later. So fetch a new version of deb package directly.
> Please note it has a dependency o
Hi Michael,
On Fri, Oct 25, 2019 at 7:28 PM Michael Walle wrote:
>
> Provide functions to read and write the Atheros debug registers.
>
> Signed-off-by: Michael Walle
This series is adding too much size to several of the boards' SPL it seems.
https://travis-ci.org/jhershbe/u-boot/builds/620804
On Tue, Nov 19, 2019 at 2:47 PM Diego Rondini
wrote:
>
> Orangepi Zero Plus 2 is an open-source single-board computer, available
> in two Allwinner SOC variants, H3 and H5. We add support for H3 variant
> here, as the H5 is already supported.
>
> H3 Orangepi Zero Plus 2 has:
> - Quad-core Cortex-A
Hi Tom, Matthias,
> The code for handing file overwrite incorrectly assumed that the file
> on disk is always contiguous. This resulted in corrupting disk
> structure every time when write to existing fragmented file happened.
> Fix this by adding proper check for cluster discontinuity and adjust
On 04/12/2019 22:28, Heinrich Schuchardt wrote:
> On 12/4/19 5:52 PM, matthias@kernel.org wrote:
>> From: Matthias Brugger
>>
>> Up to now we only update the DRAM banks when we are define
>> CONFIG_BCM2711. But our one binary approach uses a config that supports
>> BCM2837 and BCM2711. As a
Hi,
I would like to ask if it is possible to source a script after
verifying its signature.
Currently I've been able to source a script from a signed FIT image,
before doing "bootm", with:
source :
But this way the signature is not checked yet, so the script cannot be trusted.
According to the d
Many boards use only single depth configuration, for such boards
there is some unused code in video and console uclass routines.
Add guards to avoid dead code.
Signed-off-by: Anatolij Gustschin
---
drivers/video/vidconsole-uclass.c | 6 ++
drivers/video/video-uclass.c | 4
2 files
Many boards do not use all selected framebuffer depth
configurations, for such boards there is some unused
code in video and console uclass routines. Make depth
specific code optional to avoid dead code and slightly
reduce binary size. Also make ANSI code optional for
the same reason. When i.e. usi
On 12/4/19 11:42 PM, Heinrich Schuchardt wrote:
Function fetch_tftp_file() in test/py/tests/test_efi_loader.py expects that
the dictionary describing a file contains an entry 'addr' specifying the
loading address. Otherwise it defaults to the start of RAM. On
qemu_arm64_defconfig and qemu_arm_def
From: Matthias Brugger
The rpi_4_32b_defconfig states that only one DRAM bank is present. This
leads to a wrong configuration of the available DRAM. Fix this by
setting the DRAM bank config accordingly.
Fixes: 193279d784 ("RPI: Add defconfigs for rpi4 (32/64)")
Signed-off-by: Matthias Brugger
From: Matthias Brugger
Up to now we only update the DRAM banks when we are define
CONFIG_BCM2711. But our one binary approach uses a config that supports
BCM2837 and BCM2711. As a result we only see one gibibyte of RAM on
Raspberry Pi 4, even if it has more RAM.
Fix this by calling dram_init_bank
From: Matthias Brugger
To update the dram bank information from device-tree we use
fdtdec_decode_ram_size() which expectes the the size-cells and
address-cells to be defined in the memory node. For normal system RAM
these values are defined in the root node. When the values differ from
the defaul
On Thu, Dec 5, 2019 at 1:19 AM Heinrich Schuchardt wrote:
>
> On 11/6/19 12:07 AM, Joe Hershberger wrote:
> > On Tue, Nov 5, 2019 at 5:49 AM Heinrich Schuchardt
> > wrote:
> >>
> >> sandbox_defconfig does not compile using GCC 9.2.1:
> >>
> >> net/net.c: In function ‘net_process_received_packet’
On 05/12/2019 17:52, Lukasz Majewski wrote:
> Hi Tom, Matthias,
>
>> The code for handing file overwrite incorrectly assumed that the file
>> on disk is always contiguous. This resulted in corrupting disk
>> structure every time when write to existing fragmented file happened.
>> Fix this by add
On Thu, 5 Dec 2019 18:15:49 +0100
Anatolij Gustschin ag...@denx.de wrote:
> Many boards do not use all selected framebuffer depth
> configurations, for such boards there is some unused
> code in video and console uclass routines. Make depth
> specific code optional to avoid dead code and slightly
On Thu, Dec 05, 2019 at 06:58:15PM +0100, Matthias Brugger wrote:
>
>
> On 05/12/2019 17:52, Lukasz Majewski wrote:
> > Hi Tom, Matthias,
> >
> >> The code for handing file overwrite incorrectly assumed that the file
> >> on disk is always contiguous. This resulted in corrupting disk
> >> struct
On Tue, Dec 3, 2019 at 6:35 AM Ben Wolsieffer wrote:
>
> On NixOS, cross compiled kernels have long suffixes that cause them to
> exceed the current maximum path length. The PXE/TFTP max path length is
> used for extlinux.conf support as well, which is where this problem
> usually manifest's itsel
On Sun, Nov 10, 2019 at 08:23:15AM -0800, Thomas Hebb wrote:
> Signed-off-by: Thomas Hebb
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Sun, Nov 10, 2019 at 06:33:40AM -0600, Adam Ford wrote:
> SPL has limited available resources, and the performance between
> ARM and Thumb isn't that significant.
>
> This patch builds using Thumb instruction set to reduce the code
> size by nearly 6K.
>
> Original:
>text data
On Wed, Nov 13, 2019 at 07:42:00AM -0600, Adam Ford wrote:
> The da850-evm doesn't have the boot pins configured in a way
> to make MMC/SD booting an option, and MMC/SD support is not
> enabled in SPL. Therefore, there is no need to support raw mode
> mmc/sd support in SPL.
>
> This patch disabl
On Mon, Nov 25, 2019 at 05:18:20PM +0100, Giulio Benetti wrote:
> At the moment entry_point is set to image_get_load(header) that sets it
> to "load address" instead of "entry point", assuming entry_point is
> equal to load_addr, but it's not true. Then load_addr is set to
> "entry_point - header_
On Tue, Nov 26, 2019 at 05:29:31PM +0900, AKASHI Takahiro wrote:
> Unlink test for FAT file system seems to fail at test_unlink2.
> (When I added this test, I haven't seen any errors though.)
> for example,
> ===8<===
> fs_obj_unlink = ['fat', '/home/akashi/tmp/uboot_sandbox_test/128MB.fat32.img']
On Tue, Nov 26, 2019 at 05:28:49PM +0900, AKASHI Takahiro wrote:
> # This is actually a resent patch of
> # [1] https://lists.denx.de/pipermail/u-boot/2019-May/369170.html
>
> Two test cases are added under test_fs_ext:
> test case 10: for root directory
> test case 11: for non-root direc
On Tue, Nov 26, 2019 at 05:19:34PM +0100, Jorge Ramirez-Ortiz wrote:
> The mmc CID value is one of the input parameters used to provision the
> RPMB key. The trusted execution environment expects this value to be
> specified in big endian format.
>
> Before this fix, on little endian systems, the
On Sun, Dec 01, 2019 at 05:45:18PM +0100, Michael Walle wrote:
> PCI devices may be disabled in the device tree. Devices which are probed
> by the device tree handle the "status" property and are skipped if
> disabled. Devices which are probed by the PCI enumeration don't check
> that property. Fi
On Mon, Dec 02, 2019 at 10:24:16AM +0100, Lukasz Majewski wrote:
> This define indicates if DM_GPIO shall be supported in SPL. This allows
> proper operation of DM converted GPIO drivers in SPL, which use
> boards.
>
> Signed-off-by: Lukasz Majewski
Applied to u-boot/master, thanks!
--
Tom
On Mon, Dec 02, 2019 at 05:33:22PM +0100, Philippe Reynes wrote:
> The command cp fails on sandbox because the address is used
> directly. To fix this issue, we call the function map_sysmem
> to translate the address.
>
> Signed-off-by: Philippe Reynes
Applied to u-boot/master, thanks!
--
Tom
On Mon, Dec 02, 2019 at 03:45:50PM +0100, Philippe Reynes wrote:
> The command iminfo fails on sandbox because the address
> is used directly. To fix this issue, we call the function
> map_sysmem to translate the address.
>
> Signed-off-by: Philippe Reynes
Applied to u-boot/master, thanks!
--
Hi Diego,
> Hi,
>
> I would like to ask if it is possible to source a script after
> verifying its signature.
>
> Currently I've been able to source a script from a signed FIT image,
> before doing "bootm", with:
> source :
> But this way the signature is not checked yet, so the script cannot
>
From: Vladimir Oltean
To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.
If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MO
From: Vladimir Oltean
Signed-off-by: Vladimir Oltean
Acked-by: Joe Hershberger
---
drivers/net/phy/atheros.c | 69 +++
1 file changed, 41 insertions(+), 28 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 537c1a9125..c0c
From: Vladimir Oltean
Delete the extraneous write to debug reg 5 that enables Tx delay
When the driver was originally introduced in commit "6027384a phylib:
Add Atheros AR8035 GETH PHY support", the Tx delay was being
unconditionally enabled.
Then during "2ec4d10b phy: atheros: add support for
Provide functions to read and write the Atheros debug registers.
Signed-off-by: Michael Walle
---
drivers/net/phy/atheros.c | 57 ---
1 file changed, 41 insertions(+), 16 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 5f
Signed-off-by: Michael Walle
---
drivers/net/phy/atheros.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 01953a1390..5ff5875d3d 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -2
From: Vladimir Oltean
Also take the opportunity to use the phy_read_mmd and phy_write_mmd
convenience functions.
Signed-off-by: Vladimir Oltean
Acked-by: Joe Hershberger
---
drivers/net/phy/atheros.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/driv
[RESEND because I've forgot to add the mailinglist. Sorry!]
This patch series superseeds the following two:
>From Vladimir Oltean
https://patchwork.ozlabs.org/cover/1031360/
>From me:
https://patchwork.ozlabs.org/cover/1184507/
Although the first is marked as accepted into u-boot-net I guess
The upper bits are all the OUI.
Signed-off-by: Michael Walle
---
drivers/net/phy/atheros.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 3cc162828c..01953a1390 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/n
From: Vladimir Oltean
Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
the other bit positions, just like the other PHYs in the family do.
Therefore, it is not necessary to hardcode the reserved values, but
instead simply follow the read-modify-write procedure from the commo
Signed-off-by: Michael Walle
---
drivers/net/phy/atheros.c | 38 ++
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 660dcd9491..22035c2496 100644
--- a/drivers/net/phy/atheros.c
+++ b/d
Add support for configuring the CLK_25M pin as well as the RGMII I/O
voltage by the device tree.
By default the AT803x PHYs outputs the 25MHz clock of the XTAL input.
But this output can also be changed by software to other frequencies.
This commit introduces a generic way to configure this output
We can configure the clock output in the device tree. Disable the
hardcoded one in here. This is highly board-specific and should have
never been enabled in the PHY driver.
If bisecting shows that this commit breaks your board it probably
depends on the clock output of your Atheros AR8035 PHY. Ple
Now that this tool has a 'quiet' flag, use it.
Signed-off-by: Simon Glass
---
tools/buildman/control.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index c55a65d0c3..3b41d7b26a 100644
--- a/tools/buildman/control.py
+
The two functions are now exactly the same, remove one of them.
Signed-off-by: Michael Walle
---
drivers/net/phy/atheros.c | 30 +++---
1 file changed, 3 insertions(+), 27 deletions(-)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index 208b06d3c7..2
We don't really need buildman to print this every time it runs. Add a flag
to run quietly, that buildman can use.
Signed-off-by: Simon Glass
---
tools/genboardscfg.py | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/tools/genboardscfg.py b/tools/genboardscfg.py
ind
At present buildman looks at toolchains, then commits and then boards.
Move the board processing up above the commit processing, since it relates
to the toolchain code. This will make it easier to check the toolchains
needed for a board without processing commits first.
Signed-off-by: Simon Glass
Sometimes it is useful for external tools to use buildman to provide the
toolchain information. Add an -a option which shows the value to use for
the ARCH environment variable, and -A which does the same for
CROSS_COMPILE
Signed-off-by: Simon Glass
---
tools/buildman/README | 3 +++
tool
Am 2019-11-30 02:11, schrieb Joe Hershberger:
On Fri, Oct 25, 2019 at 7:28 PM Michael Walle wrote:
Provide functions to read and write the Atheros debug registers.
Signed-off-by: Michael Walle
Acked-by: Joe Hershberger
Sorry this was superseeded by
https://patchwork.ozlabs.org/project/
Am 2019-11-30 02:11, schrieb Joe Hershberger:
On Fri, Oct 25, 2019 at 7:28 PM Michael Walle wrote:
Provide functions to read and write the Atheros debug registers.
Signed-off-by: Michael Walle
Acked-by: Joe Hershberger
Sorry this series superseeded by
https://patchwork.ozlabs.org/proje
Hello,
I need to reconfigure PCIe settings to connect a GPU. From config header
files, the variables I changed are below. I did exact same changes to
linux .dts file.
But when I power on the board, u-boot is freezing during gpu driver
initialization (after reading BAR registers). I also tried so
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