[U-Boot] [PATCH v8 00/19] Add Intel Agilex SoC support

This is 8th version of patchset to add Intel Agilex SoC[1] support. This patchset needs to apply after patchset in [2] for manager driver struct to defines conversion and [3] for enable cache driver build in SPL. Patch status: Have changes: Patch 12, 17 Other patches unchanged. Detail changelog

[U-Boot] [PATCH v8 01/19] arm: socfpga: agilex: Add base address for Intel Agilex SoC

Add base address for Intel Agilex SoC. Reuse base_addr_s10.h for Agilex, only one base address is different from S10. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v2: - Reuse base_addr_s10.h and add #ifdef Agilex for SOCFPGA_FW_MPU_DDR_SCR_ADDRESS --- arch/arm/mach-socfpga/i

[U-Boot] [PATCH v8 03/19] arm: socfpga: Move Stratix10 and Agilex reset manager common code

Move Stratix10 and Agilex reset manager common code to reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*. Remove unused RSTMGR_XXX defines. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v5: - Remove reset_manager_s10.h and use reset_manager_soc64.h directly. v4: - Chang

[U-Boot] [PATCH v8 02/19] arm: socfpga: Move firewall code to firewall file

Move firewall related code to new firewall.c, to share code in Stratix 10 and Agilex. SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC to allow DMA transfer to OCRAM. Signed-off-by: Ley Foon Tan Reviewed-by: Simon Goldschmidt --- v4: - Move SYSMGR_DMA* to firewall.c v3

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