On Mon, Oct 7, 2019 at 6:37 AM Heinrich Schuchardt wrote:
>
> With the __packed attribute sandbox_defconfig cannot be compiled with GCC
> 9.2.1:
>
> fs/cbfs/cbfs.c: In function ‘file_cbfs_fill_cache’:
> fs/cbfs/cbfs.c:164:16: error: taking address of packed member of
> ‘struct cbfs_cachenode’ may
On Mon, Oct 28, 2019 at 11:27 AM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> >
> > This entry is used to hold an Intel FSP-S (Firmware Support Package
> > Silicon init) binary. Add support for this in binman.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Change
On Mon, Oct 28, 2019 at 11:27 AM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> >
> > This entry is used to hold an Intel FSP-T (Firmware Support Package
> > Temp-RAM init) binary. Add support for this in binman.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Chang
On Mon, Oct 28, 2019 at 11:27 AM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> >
> > At present binman adds the image base address to the symbol value before
> > it writes it to the binary. This is not correct since the symbol value
> > itself (e.g. image position) has
On Mon, Oct 28, 2019 at 11:27 AM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> >
> > This comment references the wrong FSP component. Fix it.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in v3: None
> > Changes in v2: None
> >
> > tools/binman/etype/int
On Mon, Oct 28, 2019 at 12:45 PM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> >
> > At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
> > is included in SPL/TPL without any control for boards. Some boards may
> > want to disable this to reduce code
On Mon, Oct 28, 2019 at 1:54 PM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> >
> > At present the name of the image comes first in the linker-list symbol
> > used. This means that the name of the function sets the sort order, which
> > is not the intention.
> >
> > Up
On Mon, Oct 28, 2019 at 1:59 PM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> >
> > Add a note about the driver name in the of-platdata documentation since
> > the naming must follow the compatible string.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in
On Sat, Nov 2, 2019 at 12:13 PM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> >
> > On x86 platforms the SPI flash can be mapped into memory so that the
> > contents can be read with normal memory accesses.
> >
> > Add a new SPI method to find the location of the SPI f
On Mon, Oct 28, 2019 at 2:34 PM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> >
> > We have the ability to enforce a maximum size for SPL but not yet for TPL.
> > Add a new option for this.
> >
> > Document the size check macro while we are here.
> >
> > Signed-off-by:
On Mon, Oct 28, 2019 at 3:12 PM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> >
> > This function can be called before the timer is set up. Make sure that the
> > init function is called so that it works correctly.
> >
> > This is needed so that bootstage can work corr
On Mon, Oct 28, 2019 at 3:12 PM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:39 AM Simon Glass wrote:
> >
> > At present the value of the timer base is used to determine whether the
> > timer has been set up or not. It is true that the timer is essentially
> > never exactly 0 when it is read. H
On Mon, Oct 28, 2019 at 3:12 PM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:40 AM Simon Glass wrote:
> >
> > The x86 power unit handles power management. Support initing this device
> > which is modelled as a new type of system controller since there are no
> > operations needed.
> >
> > Signe
On Mon, Oct 28, 2019 at 3:12 PM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:40 AM Simon Glass wrote:
> >
> > In TPL we try to minimise code size so do not include the PCI subsystem.
> > We can use fixed BARs and drivers can directly program the devices that
> > they need.
> >
> > However we do
On Mon, Oct 28, 2019 at 3:50 PM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:40 AM Simon Glass wrote:
> >
> > For TPL we only need to set up the features and identify the CPU to a
> > basic level. Add a function to handle that.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in v3:
On Sat, Nov 2, 2019 at 1:52 PM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:40 AM Simon Glass wrote:
> >
> > We don't need to do this and it is done (in more detail) in U-Boot proper.
> > Drop this to save code space.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in v3: None
> > C
On Sat, Nov 2, 2019 at 1:52 PM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:40 AM Simon Glass wrote:
> >
> > We already a message indicating that U-Boot is about to jump to SPL, so
> > make this one a debug() to reduce code size.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in v3
On Mon, Oct 28, 2019 at 3:52 PM Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:40 AM Simon Glass wrote:
> >
> > At present we call spl_init() before identifying the CPU. This is not a
> > good idea - e.g. if bootstage is enabled then it will try to set up the
> > timer which works better if the C
On Sat, Nov 02, 2019 at 10:19:02AM +0530, Jagan Teki wrote:
> roc-rk3399-pc_defconfig is committed in below
>
> commit <8a681f4c5aa15db51ad0209734859c9fe7c29cfd> ("rockchip: rk3399:
> Add ROC-RK3399-PC support")
>
> which doesn't follow the existing defconfigs on rk3399.
>
> So, rename as follow
Hi Tom,
When I build Simon's patches (the one I applied to u-boot-x86 today),
I noticed that the build results for board "tbs2910" in gitlab-ci and
azure are different.
On gitlab-ci [1], the build fails with error message:
arm: + tbs2910
+u-boot.imx exceeds file size limit:
+ limit:
On Sat, Nov 02, 2019 at 09:02:36PM +0800, Bin Meng wrote:
> Hi Tom,
>
> When I build Simon's patches (the one I applied to u-boot-x86 today),
> I noticed that the build results for board "tbs2910" in gitlab-ci and
> azure are different.
>
> On gitlab-ci [1], the build fails with error message:
>
Am 2019-05-15 16:58, schrieb Tom Rini:
On Fri, May 10, 2019 at 09:50:45PM +, Joe Hershberger wrote:
Hi Vladimir and Tom,
On Thu, May 9, 2019 at 7:51 AM Vladimir Oltean
wrote:
>
> On 09.05.2019 02:05, Vladimir Oltean wrote:
> > On 5/9/19 1:55 AM, Tom Rini wrote:
> >> On Wed, May 08, 2019
Hi Tom,
On Sat, Nov 2, 2019 at 9:05 PM Tom Rini wrote:
>
> On Sat, Nov 02, 2019 at 09:02:36PM +0800, Bin Meng wrote:
> > Hi Tom,
> >
> > When I build Simon's patches (the one I applied to u-boot-x86 today),
> > I noticed that the build results for board "tbs2910" in gitlab-ci and
> > azure are di
This series adds a driver for the Cr50 security chip and enables it on
coral. This supports the 'tpm' command.
This series is built on the pending 'apollolake' series.
Simon Glass (7):
coral: Update i2c and rtc status
tpm: Add more TPM2 definitions
tpm: Add a driver for H1/Cr50
pci: i2c:
H1 is a Google security chip present in recent Chromebooks, Pixel phones
and other devices. Cr50 is the name of the software that runs on H1 in
Chromebooks.
This chip is used to handle TPM-like functionality and also has quite a
few additional features.
Add a driver for this.
Signed-off-by: Simo
Add definitions for access and status.
Need to drop the mixed case.
Signed-off-by: Simon Glass
---
include/tpm-v2.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/include/tpm-v2.h b/include/tpm-v2.h
index ae00803f6d..d53d2e4023 100644
--- a/include/tpm-v2.
These are actually working correctly, so update the status.
Signed-off-by: Simon Glass
---
doc/board/google/chromebook_coral.rst | 2 --
1 file changed, 2 deletions(-)
diff --git a/doc/board/google/chromebook_coral.rst
b/doc/board/google/chromebook_coral.rst
index c583ac2b27..b010cc1ded 10064
Enable TPM2 so that we can use cr50.
Signed-off-by: Simon Glass
---
configs/chromebook_coral_defconfig | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/configs/chromebook_coral_defconfig
b/configs/chromebook_coral_defconfig
index 6b586ef3c7..43fb94458b 100644
--- a/conf
Add a compatible string for this driver so that it can have children.
Signed-off-by: Simon Glass
---
drivers/i2c/dw_i2c_pci.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/i2c/dw_i2c_pci.c b/drivers/i2c/dw_i2c_pci.c
index 34cdc7bf59..193ad5225f 100644
--- a/drivers/i2c/dw_i2
This printf() should not be there.
Signed-off-by: Simon Glass
---
drivers/i2c/designware_i2c.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 54e4a70c74..b12ad02a43 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/
Add a node to the device tree for Cr50. We want this to be on i2c port 2
so add 0 and 1 as well to make this work.
Signed-off-by: Simon Glass
---
arch/x86/dts/chromebook_coral.dts | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/x86/dts/chromebook_coral.dts
b
On Sat, Nov 02, 2019 at 09:17:32PM +0800, Bin Meng wrote:
> Hi Tom,
>
> On Sat, Nov 2, 2019 at 9:05 PM Tom Rini wrote:
> >
> > On Sat, Nov 02, 2019 at 09:02:36PM +0800, Bin Meng wrote:
> > > Hi Tom,
> > >
> > > When I build Simon's patches (the one I applied to u-boot-x86 today),
> > > I noticed
On Sat, Nov 02, 2019 at 02:17:28PM +0100, Michael Walle wrote:
> Am 2019-05-15 16:58, schrieb Tom Rini:
> > On Fri, May 10, 2019 at 09:50:45PM +, Joe Hershberger wrote:
> > > Hi Vladimir and Tom,
> > >
> > > On Thu, May 9, 2019 at 7:51 AM Vladimir Oltean
> > > wrote:
> > > >
> > > > On 09.05.
On Sat, 2 Nov 2019 at 16:12, Tom Rini wrote:
>
> On Sat, Nov 02, 2019 at 02:17:28PM +0100, Michael Walle wrote:
> > Am 2019-05-15 16:58, schrieb Tom Rini:
> > > On Fri, May 10, 2019 at 09:50:45PM +, Joe Hershberger wrote:
> > > > Hi Vladimir and Tom,
> > > >
> > > > On Thu, May 9, 2019 at 7:51
On Sat, Nov 02, 2019 at 04:30:11PM +0200, Vladimir Oltean wrote:
> On Sat, 2 Nov 2019 at 16:12, Tom Rini wrote:
> >
> > On Sat, Nov 02, 2019 at 02:17:28PM +0100, Michael Walle wrote:
> > > Am 2019-05-15 16:58, schrieb Tom Rini:
> > > > On Fri, May 10, 2019 at 09:50:45PM +, Joe Hershberger wrot
Hi Bin,
On Sat, Nov 2, 2019 at 3:03 PM Bin Meng wrote:
>
> Hi Tom,
>
> When I build Simon's patches (the one I applied to u-boot-x86 today),
> I noticed that the build results for board "tbs2910" in gitlab-ci and
> azure are different.
>
> On gitlab-ci [1], the build fails with error message:
>
>
On Sat, Nov 02, 2019 at 11:54:44AM +0800, Bin Meng wrote:
> On Sat, Nov 2, 2019 at 5:48 AM Tom Rini wrote:
> >
> > Now that we have buildman telling genboards.cfg to use an output
> > directory we need to ensure that it exists.
> >
> > Cc: Bin Meng
> > Cc: Simon Glass
> > Fixes: bc750bca1246 ("t
Hi Bin,
On Mon, 28 Oct 2019 at 00:47, Bin Meng wrote:
>
> Hi Simon,
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> >
> > When device-tree compilation fails it is sometimes tricky to see which
> > line is broken, since the input file to dtc is a pre-processed version
> > of the device
Hi Bin,
On Mon, 28 Oct 2019 at 00:16, Bin Meng wrote:
>
> Hi Simon,
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> >
> > This reverts commit 96ac4def8b6686de8566b91419ce98cd5765079b.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > Changes in v3: None
> > Changes in v2: None
> >
>
Also align the fspi node with the kernel one. There is actually no driver
which would match "nxp,dn-fspi".
Signed-off-by: Michael Walle
---
changes since v1:
- none
arch/arm/dts/fsl-ls1028a.dtsi | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/fsl
Hi BIn,
On Mon, 28 Oct 2019 at 01:27, Bin Meng wrote:
>
> Hi Simon,
>
> On Mon, Oct 21, 2019 at 11:40 AM Simon Glass wrote:
> >
> > Most of the timer-calibration methods are not needed on recent Intel CPUs
> > and just increase code size. Add an option to use the known-good way to
> > get the cl
This is a port of the kernel's spi-nxp-fspi driver. It uses the new
spi-mem interface and does not expose the more generic spi-xfer
interface. The source was taken from the v5.3-rc3 tag.
The port was straightforward:
- remove the interrupt handling and the completion by busy polling the
contro
From: AKASHI Takahiro
Currently, a whole disk without any partitions is not associated
with EFI_SIMPLE_FILE_SYSTEM_PROTOCOL. So even if it houses some
file system, there is a chance that we may not be able to access
it, particularly, when accesses are to be attempted after searching
that protocol
On Sat, Nov 2, 2019 at 4:01 PM Simon Glass wrote:
>
> H1 is a Google security chip present in recent Chromebooks, Pixel phones
> and other devices. Cr50 is the name of the software that runs on H1 in
> Chromebooks.
>
> This chip is used to handle TPM-like functionality and also has quite a
> few a
Hi Bin,
On Fri, 1 Nov 2019 at 22:14, Bin Meng wrote:
>
> On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> >
> > Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
> > top of 32-bit address space, so that it can be executed in place and read
> > simply by copying from
Hi Igor,
On Sat, Nov 2, 2019 at 11:26 PM Igor Opaniuk wrote:
>
> Hi Bin,
>
> On Sat, Nov 2, 2019 at 3:03 PM Bin Meng wrote:
> >
> > Hi Tom,
> >
> > When I build Simon's patches (the one I applied to u-boot-x86 today),
> > I noticed that the build results for board "tbs2910" in gitlab-ci and
> >
Hi Simon,
On Sat, Nov 2, 2019 at 5:38 PM Bin Meng wrote:
>
> On Mon, Oct 28, 2019 at 12:45 PM Bin Meng wrote:
> >
> > On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> > >
> > > At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
> > > is included in SPL/TPL without any co
Hi Simon,
On Sun, Nov 3, 2019 at 5:04 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Fri, 1 Nov 2019 at 22:14, Bin Meng wrote:
> >
> > On Mon, Oct 21, 2019 at 11:33 AM Simon Glass wrote:
> > >
> > > Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
> > > top of 32-bit address
Hi Tom,
This PR includes the following changes for x86:
- Add support for Intel FSP-S and FSP-T in binman
- Correct priority selection for image loaders for SPL
- Add a size check for TPL
- Various small SPL/TPL bug fixes and changes
- SPI: Add support for memory-mapped flash
The following chang
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