Hi Simon:
Simon Glass 于2018年8月30日周四 上午8:42写道:
> On 7 August 2018 at 05:44, Andy Yan wrote:
> > Memory region for fdt should be reserved, or they
> > may be allocated by other module via lmb_alloc.
> > Then the fdt data will be destroy.
> >
> > We found a case on a board with 64MB DRAM like bell
On Fri, Oct 5, 2018 at 6:26 PM Aleksandr Aleksandrov
wrote:
>
> Emlid Neutis N5 is a SoM based on Allwinner H5, has a WiFi & BT
> module, DDR3 RAM and eMMC.
>
> - add neutis-devboard target to dtb makefile
> - add dtsi file for Neutis N5 needs
> - add config file for Neutis N5 Dev board
>
> Signed
On Mon, Oct 8, 2018 at 1:08 PM Maxime Ripard wrote:
>
> On Sat, Oct 06, 2018 at 11:23:32PM +0800, Icenowy Zheng wrote:
> > Currently the DRAM bus gate and reset is changed at the same time in
> > H6 DRAM initialization code, which disobeys the user manual's
> > programming guide.
> >
> > Fix the s
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