Hi Simon,
On 11/10/2017 07:16 AM, Simon Glass wrote:
On 7 November 2017 at 09:18, Tuomas Tynkkynen wrote:
Currently, if the user has compiled the libfdt Python module from dtc
upstream to a non-default location, it cannot be used because the
'PYTHONPATH=tools' assignment wipes out the user's P
From: Rick Chen
ATCSPI200 is Andestech SPI IP which is embedded in
AE3XX and AE250 platforms.So rename it as atcspi200
will be more reasonable to be used in different
platforms in the future.
Rick Chen (3):
spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spi
nds32: defconfig: Rename NDS_A
From: Rick Chen
atcspi200 is Andestech spi ip which is embedded in
AE3XX and AE250 platforms. So rename as atcspi200
will be more reasonable to be used in different
platforms.
Signed-off-by: Rick Chen
---
drivers/spi/Kconfig | 10 +-
drivers/spi/Makefile|2 +-
drivers/spi
From: Rick Chen
Modify Andestech ae3xx board defconfig NDS_AE3XX
as ATCSPI200 for spi driver renaming.
Signed-off-by: Rick Chen
---
configs/adp-ae3xx_defconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig
index
From: Rick Chen
Add a document to describe Andestech atcspi200 spi and
binding information.
Signed-off-by: Rick Chen
---
doc/device-tree-bindings/spi/spi-atcspi200.txt | 37
1 file changed, 37 insertions(+)
create mode 100644 doc/device-tree-bindings/spi/spi-atcspi2
Putting board_nand_init() function inside NAND driver was not appropriate
due to it doesn't allow board vendor to customise their NAND
initialization code such as adding NAND lock/unlock code.
This commit was to move the board_nand_init() function from NAND driver
to board.c file. This allow custo
Hi Vikas
On 11/14/2017 11:16 PM, Vikas MANOCHA wrote:
> Hi Patrice,
>
> Cheers,
> Vikas
>
>> -Original Message-
>> From: Patrice CHOTARD
>> Sent: Tuesday, November 14, 2017 12:41 AM
>> To: Vikas MANOCHA ; u-boot@lists.denx.de;
>> albert.u.b...@aribaud.net; s...@chromium.org
>> Cc: Patri
Hi,
Here is a set of patches that have been sitting in some variations for
quite some time now.
This is mostly to ease the eMMC (and MMC, to some extent) flashing
using fastboot that in turn rely on GPT.
The Allwinner SoCs need to have the SPL located right in the middle of
a traditional GPT, at
The SPL must be located at 8kB (16 sectors) offset. That's right in the
middle of the GPT, so we need to define a smaller amount of partitions to
accomodate for that location.
Signed-off-by: Maxime Ripard
---
disk/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/disk/Kconfig b/disk/Kc
On some SoCs, the SPL needs to be located right in the middle of the GPT
partition entries.
One way to work around that is to create partition entries for a smaller
number of partitions to accomodate with where the SPL will be. Create a
Kconfig option to allow to do that.
Signed-off-by: Maxime Ri
The partitions variable is especially useful to create a partition table
from U-Boot, either directly from the U-Boot shell, or through flashing
tools like fastboot and its oem format command.
This is especially useful on devices with an eMMC you can't take out to
flash from another system, and bo
Now that more and more devices are built using eMMC, providing a way to
easily flash the system without too much hassle seems like a right thing to
do.
Since fastboot is the most deployed tool to do that these days, we can just
rely on it to provide a way to flash the various components in the sys
Forgot to Cc ML. Done now.
Le 15/11/2017 à 11:14, Guillaume Gardet a écrit :
Hello,
I tested U-Boot v2017.09 on a Samsung Snow (Chromebook ARM) and while mmc0
(internal eMMC) is working fine, mmc1 (external SD slot) does not work.
I get the following error for 'mmc dev 1' command:
mmc_ini
Le 15/11/2017 à 11:22, Guillaume Gardet a écrit :
Forgot to Cc ML. Done now.
Le 15/11/2017 à 11:14, Guillaume Gardet a écrit :
Hello,
I tested U-Boot v2017.09 on a Samsung Snow (Chromebook ARM) and while mmc0
(internal eMMC) is working fine, mmc1 (external SD slot) does not work.
I get the
Hi,
I ran into the same issue with the cadence qspi driver and dcache as Jason
reported (in febuary, I think - I started to monitor U-Boot in july only).
May I ask what's the status here? I do need fixes for this to keep
mach-socfpga running with qspi. I currently set dcache off globally and
it w
Up to now we were able to read/write environment data from/to UBI
volumes only indirectly by gluebi driver. This driver creates NAND MTD
on top of UBI volumes, which is quite a workaroung for this use case.
Add support for direct read/write UBI volumes in order to not use
obsolete gluebi driver.
To whom may concern,
Hi, I'm writing a u-boot script that can detect whether the eFuse are
burned or not.
my script is
var = fuse read 0 5
if var == 0x999 ; then
echo "eFuses are burned"
fi
but this script is not working. Please help me to solve this problem
regards.
Old url currently returns 403; modify to url that actually works
with current state of the list server
Signed-off-by: S. Lockwood-Childs
---
README | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/README b/README
index f288176..7a4f342 100644
--- a/README
+++ b/README
@@ -5152
Hi,
On 10.11.2017 22:34, Stephen Warren wrote:
> On 11/10/2017 04:01 AM, Michal Simek wrote:
>> After adding our small zynq uboot which has hush parser off these 3 tests
>> start to failed. It is probably just coincidence that others are
>> passing without hush parser.
>
> What was the exact prob
From: Patrice Chotard
Align the RCC compatible string with the one used by kernel.
It will allow to use the same clock driver for STM32F4
and STM32F7 and to manage the differences between the 2 SoCs
Signed-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha
---
arch/arm/dts/stm32f746.dtsi | 2
From: Patrice Chotard
PWR IP is used to enable over-drive feature in
order to reach a higher frequency.
Get its base address from DT instead of hard-coded value
Signed-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha
---
arch/arm/include/asm/arch-stm32f4/stm32_pwr.h | 23 +++
From: Patrice Chotard
MMC block needs 48Mhz source clock, for that we choose
to select the SAI PLL.
Update also stm32_clock_get_rate() to retrieve the MMC
clock source needed in MMC driver.
STM32F4 uses a different RCC variant than STM32F7. For STM32F4
sdmmc clocks bit are located into dckcfgr r
From: Patrice Chotard
Add a dedicated stm32f7 compatible string to use clk_stm32f7
driver with both STM32F4 and STM32F7 SoCs.
It will be needed to manage differences between these 2 SoCs.
Signed-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha
---
drivers/clk/clk_stm32f7.c | 1 +
1 file cha
From: Patrice Chotard
Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs
rename it to a more generic clk_stm32f.c
Fix also some checkpatch errors/warnings.
Signed-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha
---
drivers/clk/Kconfig | 8
From: Patrice Chotard
STM32F4 and STM32F7 RCC clock IP are very similar.
Same driver can be used to managed RCC clock for
these 2 SoCs.
Differences between STM32F4 and F7 will be managed using
different compatible string :
_ overdrive clock is only supported by STM32F7
_ different sys_pll_psc
From: Patrice Chotard
Like STM32H7, now STM32F4/F7 clock drivers are binded by
MFD stm32_rcc driver.
This also allows to add reset support to STM32F4/F7 SoCs family.
As Reset driver is not part of SPL supported drivers, don't bind it
in case of SPL to avoid that stm32_rcc_bind() returns an error.
From: Patrice Chotard
It's the second step to prepare STM32F4 conversion to driver model and
device tree support. STM32F4 and STM32F7 RCC IPs are similar, differences
between these 2 SoCs can be managed with different compatible string and
allows to use a common clock driver.
This series updat
From: Patrice Chotard
In order to factorize code between STM32F4 and STM32F7
migrate all structs related to RCC clocks in include/stm32_rcc.h
Signed-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha
---
arch/arm/include/asm/arch-stm32f4/stm32.h | 35
arch/arm/in
From: Patrice Chotard
This node is needed to enable performance mode
when system frequency is set up to 200Mhz.
Signed-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha
---
arch/arm/dts/stm32f7-u-boot.dtsi | 4
arch/arm/dts/stm32f746.dtsi | 7 +++
2 files changed, 11 insertions
From: Patrice Chotard
STM32F4 doesn't get rcc.h file, to avoid compilation
issue, migrate RCC related defines from rcc.h to driver
file and remove rcc.h file.
Signed-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha
---
arch/arm/include/asm/arch-stm32f7/rcc.h | 31 ---
From: Patrice Chotard
This allows to add rcc MFD support to stm32f746-disco board
This rcc MFD driver manages clock and reset for STM32 SoCs family
Signed-off-by: Patrice Chotard
Reviewed-by: Vikas Manocha
---
configs/stm32f746-disco_defconfig | 4
1 file changed, 4 insertions(+)
diff -
Currently, cadence_spi_apb is broken at least on mach-socfpga:
Commits 57897c13de03ac0136d64641a3eab526c6810387 and
b63b46313ed29e9b0c36b3d6b9407f6eade40c8f added bounce buffer handling to
cadence_qspi_apb. This is the first usage of bounce buffers for non-DMA
transfer. As it turns out, bounce buf
The last two commits on this file have added bounce buffer handling
to indirect read and write transfers. However, these are cpu-only
transfers and bouncebuf seems to be written for dma transfers only
(it invalidates the dcache in bouncebuf_stop, which throws away data
copied by the cpu that are st
Bounce buffer may be used for CPU-only transfers (this is currently
the case for cadence_qspi). However, in this case, invalidating the
data cache might throw away copied data that is still in the cache
only.
To make CPU-only transfers work with bouncebuf (but still take
advantage of having aligne
Hi,
I'm currently testing v2017.11 on my x86 platform using
the xHCI interface to load images via USB keys. But if
I don't have any USB key installed, U-Boot crashes:
=> usb reset
resetting USB...
USB0: Register 7000820 NbrPorts 7
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices
Goldschmidt Simon wrote:
> Hi,
>
> I ran into the same issue with the cadence qspi driver and dcache as Jason
> reported (in febuary, I think - I started to monitor U-Boot in july only).
>
> May I ask what's the status here? I do need fixes for this to keep
> mach-socfpga running with qspi. I cur
On 11/14/2017 04:33 PM, Eugeniy Paltsev wrote:
> Add option to set spi controller clock frequency via device tree
> using standard clock bindings.
>
> Define dw_spi_get_clk function as 'weak' as some targets
> (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
> and implement dw_
On 11/14/2017 03:17 PM, Chris Brandt wrote:
> Hi Marek,
>
> On Tuesday, November 14, 2017, Marek Vasut wrote:
>> On 11/13/2017 09:51 PM, Chris Brandt wrote:
>>> Some controllers have a 32-bit data buffer register and do not allow
>>> any other access besides 32-bit read/write.
>>>
>>> Signed-off-b
Rush, Jason A wrote;:
> I don't believe the patchset I submitted for DT bindings were merged in.
I can confirm that. I'd strongly vote for them to get in as cadence_qspi
is otherwise not usable on mach socfpga.
How can I ensure a tested-by from me gets related to that patch set?
I can't reply to
On 11/15/2017 03:17 PM, Goldschmidt Simon wrote:
> Bounce buffer may be used for CPU-only transfers (this is currently
> the case for cadence_qspi). However, in this case, invalidating the
> data cache might throw away copied data that is still in the cache
> only.
>
> To make CPU-only transfers w
On 11/15/2017 05:15 PM, Goldschmidt Simon wrote:
> Rush, Jason A wrote;:
>> I don't believe the patchset I submitted for DT bindings were merged in.
>
> I can confirm that. I'd strongly vote for them to get in as cadence_qspi
> is otherwise not usable on mach socfpga.
>
> How can I ensure a teste
Marek Vasut wrote:
> Why don't you just fix the cache operations in the driver ?
This driver is copying CPU only. There are no cache operations involved!
Vignesh added the bounce buffer obviously to fix alignment issues on
his platform.
> This bounce-buffer for only CPU operations is just wasting
On 11/15/2017 05:18 PM, Goldschmidt Simon wrote:
> Marek Vasut wrote:
>> Why don't you just fix the cache operations in the driver ?
>
> This driver is copying CPU only. There are no cache operations involved!
> Vignesh added the bounce buffer obviously to fix alignment issues on
> his platform.
>
Marek Vasut wrote:
> So what alignment problems do you observe ? If you copy using the CPU
> only, why do you need the bounce buffer at all ? I don't quite get it.
Sorry for not explaining it good enough:
I don't observe any alignment problems. mach-socfpga can do unaligned
accesses as well. This
Marek Vasut wrote:
>>> I don't believe the patchset I submitted for DT bindings were merged in.
>>
>> I can confirm that. I'd strongly vote for them to get in as cadence_qspi
>> is otherwise not usable on mach socfpga.
>>
>> How can I ensure a tested-by from me gets related to that patch set?
>> I
On 2017-11-14 19:32, Otavio Salvador wrote:
> This upgrades the U-Boot from 2017.09 to 2017.11 release.
You might encounter this when building fw_printenv/setenv tools alone:
https://lists.denx.de/pipermail/u-boot/2017-November/311505.html
--
Stefan
>
> Signed-off-by: Otavio Salvador
> ---
>
LGTM.
Cheers,
Vikas
On 11/15/2017 04:14 AM, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> It's the second step to prepare STM32F4 conversion to driver model and
> device tree support. STM32F4 and STM32F7 RCC IPs are similar, differences
> between these 2 SoCs can be managed with di
On 11/15/2017 02:34 AM, Michal Simek wrote:
Hi,
On 10.11.2017 22:34, Stephen Warren wrote:
On 11/10/2017 04:01 AM, Michal Simek wrote:
After adding our small zynq uboot which has hush parser off these 3 tests
start to failed. It is probably just coincidence that others are
passing without hush
From: Fabio Estevam
Currently the MX6QDL option is selected via CONFIG_SYS_EXTRA_OPTIONS,
but it is better to select it directly via Kconfig.
Signed-off-by: Fabio Estevam
---
arch/arm/mach-imx/mx6/Kconfig | 11 +++
configs/cgtqmx6eval_defconfig | 2 +-
configs/cm_fx6_defconf
From: Fabio Estevam
SPL option is already selected via Kconfig, so remove it from the
CONFIG_SYS_EXTRA_OPTIONS line.
Signed-off-by: Fabio Estevam
---
configs/mx6sabreauto_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6s
On 15.11.17 11:11, Maxime Ripard wrote:
> The partitions variable is especially useful to create a partition table
> from U-Boot, either directly from the U-Boot shell, or through flashing
> tools like fastboot and its oem format command.
>
> This is especially useful on devices with an eMMC you
Tom,
Passed compiling on travis,
https://travis-ci.org/yorksun/u-boot/builds/302640283, the following
changes since commit c253573f3e269fd9a24ee6684d87dd91106018a5:
Prepare v2017.11 (2017-11-13 20:08:06 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-fsl-qoriq.git
f
Goldschmidt Simon Wrote:
>Marek Vasut wrote:
I don't believe the patchset I submitted for DT bindings were merged in.
>>>
>>> I can confirm that. I'd strongly vote for them to get in as cadence_qspi
>>> is otherwise not usable on mach socfpga.
>>>
>>> How can I ensure a tested-by from me gets
Date: Tue, 14 Nov 2017 10:31:56 +0100
From: Mike Looijmans
To: Wolfgang Denk , Prabhakar Kushwaha
Cc: "u-boot@lists.denx.de" ,
"joe.hershber...@ni.com"
Subject: Re: [U-Boot] ethernet: ROM MAC address vs env variable MAC
address
Message-ID: <45c912c9-ce5a-4ee0-326a-e1dadce04...@topic.
For LS1012ARDB RevD and later versions, the I2C reading for DIP
switch setting had been no longer reliable since the board was
reworked. This patch is to add hwconfig support to enable/disable
eSDHC1 manually.
Signed-off-by: Yangbo Lu
---
board/freescale/ls1012ardb/ls1012ardb.c | 29
+ York
-Original Message-
From: Yangbo Lu [mailto:yangbo...@nxp.com]
Sent: 2017年11月16日 10:28
To: u-boot@lists.denx.de; Prabhakar Kushwaha ;
Sumit Garg
Cc: Y.b. Lu
Subject: [PATCH] armv8: ls1012a: enable/disable eSDHC1 through hwconfig for RDB
For LS1012ARDB RevD and later versions, th
Dear Duncan,
In message <1814106598.1047276.1510787951...@mail.yahoo.com> you wrote:
>
> Many board manufacturers "assign" this unique MAC address by printing it on a
> sticker and sticking that on the board somewhere. It's pretty darn hard to
> read a printed sticker in software, so we have to
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