This patchset contains several works on the sunxi DesignWare DRAM
controllers.
The 1st patch made an option for H3-like DRAM controllers
(DesignWare ones), which can ease further import of alike controllers.
The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers,
in order to add V3
From: Icenowy Zheng
Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
DesignWare DRAM controller, which do not have official free DRAM
initialization code, but can use modified dram_sun8i_h3.c.
Add a invisible option for easier DRAM initialization code reuse.
Signed-off-by: Icenow
From: Icenowy Zheng
The DesignWare DRAM controller used by H3 and newer SoCs use a bit to
identify whether the DRAM is half-width.
As H3 itself come with 32-bit DRAM, the two modes of the bit used to be
named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with 16-bit DRAM
they're really 8-bit
From: Icenowy Zheng
Some DDR2 DRAM have only four banks, not eight.
Add code to detect this situation.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/dram_sunxi_dw.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sunxi_d
From: Icenowy Zheng
DRAM chip varies, and one code cannot satisfy all DRAMs.
Add options to select a timing set.
Currently only DDR3-1333 (the original set) is added into it.
Signed-off-by: Icenowy Zheng
---
arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h | 30 ++
arch/arm/mach-sunxi/Kc
From: Icenowy Zheng
The DesignWare-like DRAM code used to set the controller defaultly to
single rank mode, which makes it not able to detect the second rank.
Set the default value to dual rank, thus the rank detection code can
work and finally the rank setting will be the correct value.
Curren
From: Icenowy Zheng
Allwinner V3s features a DRAM controller like the on in H3, but with a
DDR2 DRAM.
Add support for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/Kconfig | 5 -
arch/arm/mach-sunxi/dram_sunxi_dw.c | 3 +++
2 files changed, 7 insertions(+), 1 deletion(-
From: Icenowy Zheng
Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its
timing param.
Add support for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/Kconfig | 10
arch/arm/mach-sunxi/dram_sunxi_dw.c | 2 +
arch/arm/mach-sunxi/dram_t
From: Icenowy Zheng
Some Allwinner SoCs features a DesignWare-like controller with only 16
bit bus width.
Add support for them.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Rebased on newest sunxi/next.
arch/arm/mach-sunxi/Kconfig | 17 +
arch/arm/mach-sunxi/dram
The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM
chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card
detect pin of the MicroSD slot is broken, however, it doesn't matter as
the design of SoPine didn't allow hot-swapping the MicroSD card (The
MicroSD slot is at
As we have already support for the DesignWare DRAM controller and the
integrated DDR2 chip of V3s, let's enable the SPL support for V3s.
This patch also contains the default DRAM configuration for V3s.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/Kconfig | 7 ++-
1 file changed, 6 i
From: Icenowy Zheng
Some A64 boards (SoPine and Pinebook production batch) use LPDDR3 DRAM
chips.
Add support for LPDDR3 DRAM in the DesignWare-like DRAM controller code.
Real LPDDR3 chips' support is not added yet in this commit.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/Kconfig
From: Icenowy Zheng
As we added LPDDR3 support in the former patch, we need a set of timing
info to really enable it.
Add the timing info used by stock boot0.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Added some comments suggested by Andre Przywara.
arch/arm/mach-sunxi/Kconfig
BCM63xx SPI controller is a bit tricky since it doesn't allow keeping CS
active between transfers, so I had to modify the spi_flash driver in order
to allow limiting reads.
v3: Fix bug introduced in v2: sizeof(cmd) vs len.
Also rename BCM6338 SPI driver to BCM6348 SPI since BCM6338 is a stripped
d
Command bytes are part of the written bytes and they should be taken into
account when sending a spi transfer.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v3: Fix bug introduced in v2: sizeof(cmd) vs len
v2: Introduce changes requested by Simon Glass:
- Always include
This driver manages the SPI controller present on this SoC.
Signed-off-by: Álvaro Fernández Rojas
---
v3: rename BCM6338 SPI driver to BCM6348
v2: add spi alias
arch/mips/dts/brcm,bcm6348.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm6348.dt
For some SPI controllers it's not possible to keep the CS active between
transfers and they are limited to a known number of bytes.
This splits spi_flash reads into different iterations in order to respect
the SPI controller limits.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
This driver manages the low speed SPI controller present on this SoC.
Signed-off-by: Álvaro Fernández Rojas
---
v3: no changes
v2: add spi alias
arch/mips/dts/brcm,bcm63268.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c
Instead of supporting both HW revisions of the controller in a single build,
support has been split by the selected config to save space.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Simon Glass
---
v3: rename BCM6338
This driver manages the SPI controller present on this SoC.
Signed-off-by: Álvaro Fernández Rojas
---
v3: rename BCM6338 SPI driver to BCM6348
v2: add spi alias
arch/mips/dts/brcm,bcm6338.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm6338.dt
This driver manages the SPI controller present on this SoC.
Signed-off-by: Álvaro Fernández Rojas
---
v3: no changes
v2: add spi alias
arch/mips/dts/brcm,bcm6358.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bc
It's a Spansion (s25fl064a) 8 MB SPI flash.
Signed-off-by: Álvaro Fernández Rojas
---
v3: no changes
v2: remove spi alias
arch/mips/dts/netgear,cg3100d.dts | 12
configs/netgear_cg3100d_ram_defconfig | 8
2 files changed, 20 insertions(+)
diff --git a/arch/mips/dts
This driver manages the SPI controller present on this SoC.
Signed-off-by: Álvaro Fernández Rojas
---
v3: no changes
v2: add spi alias
arch/mips/dts/brcm,bcm3380.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm3380.dtsi b/arch/mips/dts/brcm,bc
It's a Winbond (w25x32) 4 MB SPI flash.
Signed-off-by: Álvaro Fernández Rojas
---
v3: rename BCM6338 SPI driver to BCM6348
v2: remove spi alias
arch/mips/dts/sagem,f...@st1704.dts | 12
configs/sagem_f@st1704_ram_defconfig | 8
2 files changed, 20 insertions(+)
dif
BCM63xx HSSPI controller has the same issue as BCM63xx SPI controller: it
doesn't allow keeping CS active between transfers.
However, this controller allows changing CS polarities, which is used in the
linux upstream driver to manage CS as desired.
v2: Introduce changes suggested by Simon Glass:
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c
Signed-off-by: Álvaro Fernández Rojas
---
v2: Introduce changes suggested by Simon Glass:
- Split bcm63xx_hsspi_xfer() into smaller functions.
- Check possible clock errors.
- Check possible reset errors.
- Switch to
This driver manages the high speed SPI controller present on this SoC.
Signed-off-by: Álvaro Fernández Rojas
---
v2: no changes
arch/mips/dts/brcm,bcm63268.dtsi | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm6
This driver manages the SPI controller present on this SoC.
Signed-off-by: Álvaro Fernández Rojas
---
v2: no changes
arch/mips/dts/brcm,bcm6328.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
i
It's a Macronix (mx25l12805d) 16 MB SPI flash.
Signed-off-by: Álvaro Fernández Rojas
---
v2: no changes
arch/mips/dts/comtrend,ar-5387un.dts| 12
configs/comtrend_ar5387un_ram_defconfig | 8
2 files changed, 20 insertions(+)
diff --git a/arch/mips/dts/comtrend,ar-53
On 06/01/2017 02:05 PM, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> This patch adds the ST glue logic to manage the DWC3 HC
> on STiH407 SoC family. It configures the internal glue
> logic and syscfg registers.
>
> Part of this code been extracted from kernel.org driver
> (drivers/
On 06/01/2017 01:36 PM, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> Add reset_count() method to be able to get the number
> of resets contained into a resets property. This will allow
> to allocate the right amount of memory in order to keep resets
> reference. These resets referenc
On 06/01/2017 01:25 PM, Meng Dongyang wrote:
> Fix macro error of dwc2 driver, add macro definition to config force mode
> and HNP/SRP capability.
Can you please elaborate some more on the purpose of this patch ? It
seems wrong, since the driver works on systems using DWC2 as is and this
patch cha
On 06/01/2017 02:05 PM, patrice.chot...@st.com wrote:
> From: Patrice Chotard
>
> This is the generic phy driver for the picoPHY ports
> used by USB2/1.1 controllers. It is found on STiH407 SoC
> family from STMicroelectronics.
>
> Signed-off-by: Patrice Chotard
> Reviewed-by: Marek Vasut
> --
On 05/29/2017 06:00 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Enable FPGA driver build for SPL because FPGA driver is needed for SPL
> to configure and getting DDR up before loading U-boot into DDR and
> booting from there.
>
> Signed-off-by: Tien Fong Chee
The thing I fai
On 05/29/2017 06:00 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> This patch is for enabling the FPGA driver support on SPL.
>
> Signed-off-by: Tien Fong Chee
> ---
> include/configs/socfpga_common.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/configs/soc
On Fri, 2 Jun 2017 19:22:29 -0700
ali...@peloton-tech.com wrote:
> Significant changes since v2:
> -- Got rid of the need to allocate memory for the GUID string in
>do_gpt();
> -- Fixed the problems with string NULL termination in
>allocate_disk_part();
> -- Removed duplicate definition o
Hi Alison,
> From: Alison Chaiken
>
> Move MAX_SEARCH_PARTITIONS to part.h so that functions in cmd
> directory can find it. At the same time, increase the value to
> 64 since some operating systems use many, and the resources
> consumed by a larger value are minimal.
>
> Signed-off-by: Alison
Hi Eddie,
> 2017-05-31 15:12 GMT+08:00 Lukasz Majewski :
> > On Wed, 31 May 2017 10:27:23 +0800
> > Eddie Cai wrote:
> >
> >> Hi Lukasz
> >>
> >> 2017-05-29 15:51 GMT+08:00 Lukasz Majewski :
> >> > Good morning Eddie,
> >> >
> >> >> this patch enable rockusb support on rk3288 based device.
> >> >
Dear Marek,
Please find pull request for dfu repository:
The following changes since commit 46bac66b20da6d50e757bdca74703153f233090b:
sandbox: Move to use live tree (2017-06-01 07:03:17 -0600)
are available in the git repository at:
git://git.denx.de/u-boot.git
for you to fetch changes u
On 06/03/2017 07:18 PM, Lukasz Majewski wrote:
> Dear Marek,
>
> Please find pull request for dfu repository:
Pulled, thanks.
> The following changes since commit 46bac66b20da6d50e757bdca74703153f233090b:
>
> sandbox: Move to use live tree (2017-06-01 07:03:17 -0600)
>
> are available in the
Now that these symbols are in Kconfig, migrate all users. Use imply on
a number of platforms that default to having this enabled. As part of
this we must migrate some straglers for CMD_FAT and DOS_PARTITION.
Signed-off-by: Tom Rini
---
This replaces the original 5/7 and migrates everything.
R
On Fri, Jun 02, 2017 at 05:54:05PM +0530, Sekhar Nori wrote:
> Now that we have ability to enable FAT filesystem support
> through Kconfig symbols, do it for OMAP-L138 LCDK board.
>
> Signed-off-by: Sekhar Nori
> ---
> configs/omapl138_lcdk_defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
>
On Mon, May 29, 2017 at 09:06:50AM +0200, Michal Simek wrote:
> Add poweroff description to Kconfig to make it selectable
> via menuconfig.
>
> Signed-off-by: Michal Simek
> ---
>
> cmd/Kconfig | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/cmd/Kconfig b/cmd/Kconf
Signed-off-by: York Sun
---
board/freescale/mpc8541cds/MAINTAINERS | 4 ++--
board/freescale/mpc8555cds/MAINTAINERS | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/freescale/mpc8541cds/MAINTAINERS
b/board/freescale/mpc8541cds/MAINTAINERS
index d421b12..1d969f1 100
Drop support for these two legacy boards.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/Kconfig| 10 -
board/freescale/mpc8540ads/Kconfig | 12 -
board/freescale/mpc8540ads/MAINTAINERS | 6 -
board/freescale/mpc8540ads/Makefile | 11 -
board/freescale/mpc8540ads/dd
Enable DHCP command to make TFTP easier. Users don't have to use
static IP address.
Signed-off-by: York Sun
---
configs/MPC8536DS_36BIT_defconfig | 1 +
configs/MPC8536DS_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/configs/MPC8536DS_36BIT_defconfig
b/configs/MPC8536DS
Fix compiling error of "no member named 'taamin_ps'" for DDR2.
Signed-off-by: York Sun
---
drivers/ddr/fsl/interactive.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 202ad13..653bbab 100644
--- a/drivers/ddr/fsl/inte
Signed-off-by: York Sun
---
board/freescale/mpc8610hpcd/MAINTAINERS | 2 +-
board/freescale/mpc8641hpcn/MAINTAINERS | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/mpc8610hpcd/MAINTAINERS
b/board/freescale/mpc8610hpcd/MAINTAINERS
index de6ab89..8986c11 1
Enable DHCP command to make TFTP easier.
Enable DDR interactive debug by default.
Signed-off-by: York Sun
---
configs/MPC8641HPCN_defconfig | 1 +
include/configs/MPC8641HPCN.h | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641H
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