On 22/01/17 07:16, Kever Yang wrote:
> Hi Andre,
>
> On 01/20/2017 09:53 AM, Andre Przywara wrote:
>> At the moment we load two images from a FIT image: the actual U-Boot
>> image and the DTB. Both times we have very similar code to deal with
>> alignment requirement the media we load from imposes
On 22/01/17 07:08, Kever Yang wrote:
> Hi Andre,
>
> Thanks for your patches, this is great help for enable ATF on U-Boot
> SPL.
> For ATF use case, we would like to identify which one is bl31 for we
> need to
> get entry point for it while we only need load address for other image.
> Any idea
2017-01-21 18:05 GMT+09:00 Masahiro Yamada :
> - Make SPL optional for ARMv8 SoCs (main motivation is to use ATF)
> - Refactor SoC init code
> - Add PXs3 SoC support (DT, pinctrl driver, SoC code)
>
>
>
> Masahiro Yamada (11):
> ARM: uniphier: add missing static and const qualifier
> ARM:
Hi Tom,
Please pull the 2nd round of UniPhier updates for v2017.03:
- Allow to disable SPL (mainly for ATF)
- Refactor SoC init code
- Update DRAM settings
- Add PXs3 SoC support (DT, pinctrl driver, SoC code)
The following changes since commit 2d8d190c8394b43c0989cdb04a50cb48d4e1f8da:
On Sat, Jan 21, 2017 at 11:09:20PM -0500, Tom Rini wrote:
> On Sun, Jan 22, 2017 at 12:45:44PM +0900, Masahiro Yamada wrote:
> > Hi.
> >
> >
> > 2017-01-22 8:02 GMT+09:00 Tom Rini :
> > > On Sat, Jan 21, 2017 at 11:48:33AM +0100, Jagan Teki wrote:
> > >
> > >> Cc: Tom Rini
> > >> Signed-off-by:
On 01/22/2017 07:29 AM, Westergreen, Dalon wrote:
> On Sun, 2017-01-22 at 01:36 +0100, Marek Vasut wrote:
>> On 01/22/2017 12:04 AM, Westergreen, Dalon wrote:
>>>
>>> On Sat, 2017-01-21 at 20:29 +0100, Marek Vasut wrote:
On 01/21/2017 06:31 PM, Dalon Westergreen wrote:
>
>
> F
This series adds support for the network and the qspi devices found on
the stm32f746 controller and enables those devices on the
stm32f746-disco board.
Changes in v4:
- Correct commit message and add linux source file path
- Update to current master
- Fix missing newline at end of file
- Removed c
This patch adds the DTS source files needed for stm32f746-disco board
The files are based on the stm32f429/469 files from current linux
kernel.
Source for "arch/arm/dts/armv7-m.dtsi": Linux: "arch/arm/boot/dts/armv7-m.dtsi"
Signed-off-by: Michael Kurz
Acked-by: Vikas MANOCHA
---
Changes in v4
This patch adds pin control definitions for use in device tree files
The definitions are based on the stm32f746 files from current
linux kernel "include/dt-bindings/pinctrl/stm32f746-pinfunc.h".
Signed-off-by: Michael Kurz
Acked-by: Vikas MANOCHA
---
Changes in v4:
- Correct commit message and
The fmc base address is defined twice, once in fmc.h and once in stm32.h.
Fix wrong definition in stm32.h.
Remove the definiton in fmc.h.
Signed-off-by: Michael Kurz
Acked-by: Vikas Manocha
---
Changes in v4:
- Reword commit message
- Add Acked-by tag to 'fix stm32f7 sdram fmc base address'
C
Use the clock setup function defined in clock.c instead of setting the
clock bits directly in the drivers.
Remove register definitions of RCC in rcc.h as these are already
defined in the struct in stm32.h
Signed-off-by: Michael Kurz
Reviewed-by: Joe Hershberger
Reviewed-by: Vikas Manocha
---
Cleanup stm32f7 files:
- use BIT macro
- use GENMASK macro
- use rcc struct instead of macro additions
Add missing stm32f7 register in rcc struct
Signed-off-by: Michael Kurz
---
Changes in v4:
- Split struct stm32_rcc_regs into two structs (common and stm32f7 specific)
Changes in v3:
- Remove
This patch adds support for SMSC LAN8742 in phylib
Signed-off-by: Michael Kurz
Acked-by: Joe Hershberger
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Add Acked-by tag to 'net: phy: add SMSC LAN8742 phy'
drivers/net/phy/smsc.c | 12
1 file changed, 12 insertions(+
This patch enables support for the smsc phy on the
stm32f746-disco board.
Signed-off-by: Michael Kurz
Acked-by: Vikas MANOCHA
Series-changes 3:
- Add Acked-by tag to 'enable support for smsc phy on...'
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/configs/stm32f746
This patch adds support for the QSPI IP found in stm32f7 devices.
Signed-off-by: Michael Kurz
---
Changes in v4:
- Remove dts patch as the dts import patch now disables the quad interface
Changes in v3:
- Moved qspi rcc bits into rcc header
- Drop 'add missing flag to micron/stm N25Q128 flash
This patch adds glue code required for enabling the designware
mac on stm32f7 devices.
Signed-off-by: Michael Kurz
Acked-by: Joe Hershberger
---
Changes in v4: None
Changes in v3:
- Add Acked-by tag to 'add designware mac glue code for stm32'
Changes in v2:
- Replaced bit shifts and masks wit
On Fri, Jan 20, 2017 at 10:33:28PM +, Andre Przywara wrote:
> The ctype implementation (isdigit() & friends) works with an array of
> 256 Bytes - one for each character. This is pretty big in SPL terms,
> so let's replace this "bloated" implementation with a tiny version
> using C statements. T
On Sat, Jan 21, 2017 at 10:07 PM, Andy Shevchenko
wrote:
> This option useful not only for development, but for the platforms where
> U-Boot is run from custom ROM bootloader. For example, Intel Edison is
> that board.
>
> Make this option visible that platforms can select it if needed.
> --- a/a
On 01/20/2017 09:51 PM, Simon Glass wrote:
> Hi Andrew,
>
> On 12 January 2017 at 09:19, Andrew F. Davis wrote:
>> Signed-off-by: Andrew F. Davis
>> ---
>> common/spl/spl.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/common/spl/spl.c b/common/spl/spl.c
>> ind
On 01/19/2017 11:59 AM, Lokesh Vutla wrote:
>
>
> On Thursday 19 January 2017 09:29 PM, Andrew F. Davis wrote:
>> On 01/17/2017 10:14 PM, Lokesh Vutla wrote:
>>>
>>> [..snip..]
>>>
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk
am335x-bonegreen am335x-ice
On 01/20/2017 04:33 PM, Andre Przywara wrote:
> The ctype implementation (isdigit() & friends) works with an array of
> 256 Bytes - one for each character. This is pretty big in SPL terms,
> so let's replace this "bloated" implementation with a tiny version
> using C statements. This only implement
On 01/22/2017 03:58 PM, Andrew F. Davis wrote:
> On 01/20/2017 04:33 PM, Andre Przywara wrote:
>> The ctype implementation (isdigit() & friends) works with an array of
>> 256 Bytes - one for each character. This is pretty big in SPL terms,
>> so let's replace this "bloated" implementation with a ti
Add debug statements to memalign_simple to match malloc_simple.
Signed-off-by: Andrew F. Davis
---
common/malloc_simple.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/common/malloc_simple.c b/common/malloc_simple.c
index 0f6bcbcc71..611400265b 100644
--- a/common/mall
Hello all,
This series is [0] and [1] together due to a dependency. Both are
modified as suggested in the comments.
Thanks,
Andrew
[0]: https://patchwork.ozlabs.org/patch/713945/
[1]: https://patchwork.ozlabs.org/patch/715820/
Andrew F. Davis (3):
malloc_simple: Add debug statements to memal
Add a new defconfig file for the AM335x High Security EVM. This config
is specific for the case of memory device booting. Memory device booting
is handled separatly from peripheral booting on HS devices as the load
address changes.
This defconfig is the same as for the non-secure part, except for:
spl_init on some boards is called after stack and heap relocation, on
some platforms spl_relocate_stack_gd is called to handle setting the
limit to its value CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN when simple
SPL malloc is enabled during relocation. spl_init should then not
re-assign the old pre-relo
Hi Samuele
Please note that this list is usually English only.
On Fri, 2017-01-20 at 21:49 +0100, Samuele Bugs wrote:
> Buoansera in che modo è possibile resettare completamente una emmc e
> eventualmente di quali modelli samsung stiamo parlando
You may find some information about eMMC reset beh
On 22/01/17 16:09, Tom Rini wrote:
> On Fri, Jan 20, 2017 at 10:33:28PM +, Andre Przywara wrote:
>> The ctype implementation (isdigit() & friends) works with an array of
>> 256 Bytes - one for each character. This is pretty big in SPL terms,
>> so let's replace this "bloated" implementation wit
The directory structure of device tree files produced by the kernel's
'make dtbs_install' is different on ARM64, the RPi3 device tree file is
in a 'broadcom' subdirectory there.
Signed-off-by: Tuomas Tynkkynen
---
v2: Build the full DTB at compile-time, not runtime.
board/raspberrypi/rpi/rpi.c
On Sun, Jan 22, 2017 at 11:30:04PM +, André Przywara wrote:
> On 22/01/17 16:09, Tom Rini wrote:
> > On Fri, Jan 20, 2017 at 10:33:28PM +, Andre Przywara wrote:
> >> The ctype implementation (isdigit() & friends) works with an array of
> >> 256 Bytes - one for each character. This is pretty
Rename CONFIG_IMX31_PHYCORE_EET to CONFIG_TARGET_IMX31_PHYCORE_EET and
make this a distinct config target.
Signed-off-by: Tom Rini
---
arch/arm/Kconfig| 6 +-
board/imx31_phycore/Kconfig | 2 +-
configs/imx31_phycore_eet_defconfig | 3 +--
include/configs/imx31_ph
Introduce board/freescale/common/Kconfig so that we have a single place
for CONFIG options that are shared between ARM and PowerPC NXP platforms.
Cc: York Sun
Signed-off-by: Tom Rini
---
arch/arm/include/asm/fsl_secure_boot.h | 8
arch/powerpc/include/asm/fsl_secure_boot.h | 5
On Fri, Jan 20, 2017 at 8:51 PM, Simon Glass wrote:
> Hi,
>
> On 17 January 2017 at 08:50, Emmanuel Vadot wrote:
>> Add a FreeBSD option that enable the API and enable the data cache
>> command as it is needed to boot the FreeBSD loader.
>>
>> Signed-off-by: Emmanuel Vadot
>> ---
>> common/Kcon
On Sat, 2017-01-21 at 20:29 +0100, Marek Vasut wrote:
> On 01/21/2017 06:31 PM, Dalon Westergreen wrote:
> >
> > From: Dalon Westergreen
> >
> > The default values for CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
> > and CONFIG_SYS_MMCSD_FS_OS_PARTITION have changed and as
> > as result the default uboot
On Fri, Jan 20, 2017 at 8:51 PM, Simon Glass wrote:
> Hi,
>
> On 17 January 2017 at 08:50, Emmanuel Vadot wrote:
>> Add kconfig file to enable API support
>>
>> Signed-off-by: Emmanuel Vadot
>> ---
>> Kconfig | 2 ++
>> api/Kconfig | 9 +
>> 2 files changed, 11 insertions(+)
>> cre
On Sun, 2017-01-22 at 01:36 +0100, Marek Vasut wrote:
> On 01/22/2017 12:04 AM, Westergreen, Dalon wrote:
> >
> > On Sat, 2017-01-21 at 20:29 +0100, Marek Vasut wrote:
> > >
> > > On 01/21/2017 06:31 PM, Dalon Westergreen wrote:
> > > >
> > > >
> > > > From: Dalon Westergreen
> > > >
> > > >
2017-01-23 9:43 GMT+09:00 Tom Rini :
> This option should not really be user selectable. Note that on PowerPC
> we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be
> conditional on that.
>
> Signed-off-by: Tom Rini
Acked-by: Masahiro Yamada (for UniPhier)
--
Best Rega
On Sat, Jan 21, 2017 at 05:58:47PM -0500, Tom Rini wrote:
> On occasion the job that does these two build types will hit the time
> limit so split this in two.
>
> Signed-off-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
_
On Sun, Jan 22, 2017 at 09:55:58PM +0900, Masahiro Yamada wrote:
> Hi Tom,
>
> Please pull the 2nd round of UniPhier updates for v2017.03:
> - Allow to disable SPL (mainly for ATF)
> - Refactor SoC init code
> - Update DRAM settings
> - Add PXs3 SoC support (DT, pinctrl driver, SoC code)
Hi Andre,
On 01/22/2017 06:42 PM, André Przywara wrote:
On 22/01/17 07:16, Kever Yang wrote:
Hi Andre,
On 01/20/2017 09:53 AM, Andre Przywara wrote:
At the moment we load two images from a FIT image: the actual U-Boot
image and the DTB. Both times we have very similar code to deal with
alignm
Hi Andre,
On 01/22/2017 06:58 PM, André Przywara wrote:
On 22/01/17 07:08, Kever Yang wrote:
Hi Andre,
Thanks for your patches, this is great help for enable ATF on U-Boot
SPL.
For ATF use case, we would like to identify which one is bl31 for we
need to
get entry point for it while we onl
On Sun, Jan 22, 2017 at 04:19:36PM -0600, Andrew F. Davis wrote:
> spl_init on some boards is called after stack and heap relocation, on
> some platforms spl_relocate_stack_gd is called to handle setting the
> limit to its value CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN when simple
> SPL malloc is enab
On Sun, Jan 22, 2017 at 04:19:35PM -0600, Andrew F. Davis wrote:
> Add debug statements to memalign_simple to match malloc_simple.
>
> Signed-off-by: Andrew F. Davis
Reviewed-by: Tom Rini
--
Tom
signature.asc
Description: Digital signature
___
U-
These patches update the boot and os partition numbers in the
default uboot environment for a number of socfpga boards. Per
request, common environment configurations have been moved to a
shared header.
___
U-Boot mailing list
U-Boot@lists.denx.de
http
These patches update the boot and os partition numbers in the
default uboot environment for a number of socfpga boards. Per
request, common environment configurations have been moved to a
shared header.
Thanks,
Dalon
___
U-Boot mailing list
U-Boot@list
From: Dalon Westergreen
Move repeated environment settings for socfpga boards
to a common header.
The default values for the boot partition and the
OS filesystem partition have changed and as
as result the default uboot environment for socfpga
boards needs updating.
Move to using CONFIG_DEFAUL
From: Dalon Westergreen
Remove the default environment as it is now in a common
header.
Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.
Signed-off-by: Dalon Westergreen
---
configs/socfpga_de0_nano_soc_defconfig | 3 +--
include/configs/socfpga_d
From: Dalon Westergreen
Remove the default environment as it is now in a common
header.
Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.
Signed-off-by: Dalon Westergreen
---
configs/socfpga_cyclone5_defconfig | 1 +
include/configs/socfpga_c
From: Dalon Westergreen
Remove the default environment as it is now in a common
header.
Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.
Signed-off-by: Dalon Westergreen
---
configs/socfpga_arria5_defconfig | 1 +
include/configs/socfpga_arr
From: Dalon Westergreen
Remove the default environment as it is now in a common
header.
Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.
Signed-off-by: Dalon Westergreen
---
configs/socfpga_de1_soc_defconfig | 1 +
include/configs/socfpga_de1_soc.
From: Dalon Westergreen
Remove the default environment as it is now in a common
header.
Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.
Signed-off-by: Dalon Westergreen
---
configs/socfpga_sockit_defconfig | 1 +
include/configs/socfpga_sockit.h
From: Dalon Westergreen
Remove the default environment as it is now in a common
header.
Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.
Signed-off-by: Dalon Westergreen
---
configs/socfpga_sr1500_defconfig | 1 +
include/configs/socfpga_sr1500.h
Add CycloneV based Terasic DE10 Nano board. The
board is based on the DE0 Nano but has a larger
fpga.
Signed-off-by: Dalon Westergreen
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_cyclone5_de10_nano.dts | 68 +++
arch/arm/mach-socfpga/Kconfig | 7
These patches update the boot and os partition numbers in the
default uboot environment for a number of socfpga boards. Per
request, common environment configurations have been moved to a
shared header.
Changes in v3:
- Corrected error in common default environment
Thanks,
Dalon
_
From: Dalon Westergreen
Move repeated environment settings for socfpga boards
to a common header.
The default values for the boot partition and the
OS filesystem partition have changed and as
as result the default uboot environment for socfpga
boards needs updating.
Move to using CONFIG_DEFAUL
From: Dalon Westergreen
Remove the default environment as it is now in a common
header.
Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.
Signed-off-by: Dalon Westergreen
---
configs/socfpga_cyclone5_defconfig | 1 +
include/configs/socfpga_c
From: Dalon Westergreen
Remove the default environment as it is now in a common
header.
Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.
Signed-off-by: Dalon Westergreen
---
configs/socfpga_arria5_defconfig | 1 +
include/configs/socfpga_arr
From: Dalon Westergreen
Remove the default environment as it is now in a common
header.
Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.
Signed-off-by: Dalon Westergreen
---
configs/socfpga_de0_nano_soc_defconfig | 3 +--
include/configs/socfpga_d
From: Dalon Westergreen
Remove the default environment as it is now in a common
header.
Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.
Signed-off-by: Dalon Westergreen
---
configs/socfpga_de1_soc_defconfig | 1 +
include/configs/socfpga_de1_soc.
From: Dalon Westergreen
Remove the default environment as it is now in a common
header.
Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.
Signed-off-by: Dalon Westergreen
---
configs/socfpga_sr1500_defconfig | 1 +
include/configs/socfpga_sr1500.h
Hi Stefan,
On 01/21/2017 06:20 PM, Stefan Roese wrote:
> This driver implementes platform specific code for the Xenon SDHCI
> controller which is integrated in the Marvell MVEBU Armada 37xx and
> Armada 7k / 8K SoCs.
>
> History:
> This driver is ported from the Marvell U-Boot version 2015.01 whi
From: Dalon Westergreen
Remove the default environment as it is now in a common
header.
Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
to set the linux devicetree name.
Signed-off-by: Dalon Westergreen
---
configs/socfpga_sockit_defconfig | 1 +
include/configs/socfpga_sockit.h
On Monday 23 January 2017 03:49 AM, Andrew F. Davis wrote:
> Add debug statements to memalign_simple to match malloc_simple.
>
> Signed-off-by: Andrew F. Davis
Reviewed-by: Lokesh Vutla
Thanks and regards,
Lokesh
___
U-Boot mailing list
U-Boot@lis
On Monday 23 January 2017 03:49 AM, Andrew F. Davis wrote:
> Add a new defconfig file for the AM335x High Security EVM. This config
> is specific for the case of memory device booting. Memory device booting
> is handled separatly from peripheral booting on HS devices as the load
> address changes
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> Add the structures for the SDRAM controller on Arria10.
>
> Signed-off-by: Dinh Nguyen
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> ---
> arch/arm/mach-so
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> Add system manager defines for Arria10.
>
> Signed-off-by: Dinh Nguyen
> Signed-off-by: Tien Fong Chee
Acked-by: Marek Vasut
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> ---
> .../arm
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> Add arch_early_init_r function. The Arria10 has a firewall protection
> around the SDRAM and OCRAM. These firewalls are to be disabled in order
> for U-Boot to function.
Shouldn't all this happen in SPL ?
> Signed-off-by:
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> Add remaining 3 I2C base addresses for the Arria10.
>
> Signed-off-by: Dinh Nguyen
> Signed-off-by: Tien Fong Chee
> Reviewed-by: Stefan Roese
> Cc: Marek Vasut
Acked-by: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Lia
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> Add minimal support for the Arria10 SoCDK.
>
> Signed-off-by: Dinh Nguyen
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> ---
> board/altera/arria10-socdk/Kc
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> Add config for the Arria10 SoC Development Kit.
>
> Signed-off-by: Dinh Nguyen
> Signed-off-by: Tien Fong Chee
> Acked-by: Marek Vasut
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> ---
>
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
Commit message missing.
> Signed-off-by: Dinh Nguyen
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> ---
> arch/arm/Kconfig | 4 ++--
> arch/arm/ma
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> Add a defconfig file for Arria10, which does not include enabling SPL.
>
> Signed-off-by: Dinh Nguyen
> Signed-off-by: Tien Fong Chee
> Acked-by: Marek Vasut
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
>
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> The system manager on Arria10 is not used for pin muxing duties, so wrap
> these functions for GEN5 devices only.
>
> Signed-off-by: Dinh Nguyen
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc:
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
> the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
> the reading the bsel can generic.
>
> Suggested-by: Marek Vasut
>
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> Add the defines for the reset manager and some basic reset functionality.
>
> Signed-off-by: Dinh Nguyen
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> ---
>
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
> so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
> option in drivers/ddr/altera/Kconfig.
>
> Signed-off-by: Dinh Nguyen
> Sign
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> Add the Arria10 reset manager defines that is used in Linux. Change the
> license to SPDX.
>
> [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
>
> Signed-off-by: Dinh Nguyen
> Signed-off-by: Tien F
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> On the Arria10 device, the bridges are not mapped through the interconnect.
>
> Signed-off-by: Dinh Nguyen
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> ---
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> These functions are already in arch/arm/mach-socfpga/board.c
>
> Signed-off-by: Dinh Nguyen
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
Uh, wrap this into
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> There is no dependency on doing a separate clrbits first in the
> dwmac_deassert_reset function. Combine them into a single
> clrsetbits call.
>
> Signed-off-by: Dinh Nguyen
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vas
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> On the Arria10, the EMAC phy mode configuration for each EMACs is located
> in separate registers versus being in 1 register for the GEN5 devices. The
> Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.
>
> Updat
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> This is initial version of device tree for the Intel socfpga arria10
> development kit with sdmmc.
>
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> ---
> arc
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> These compat macros would be used by clock manager and pin mux drivers
> to look the required HW info from DTS for hardware initialization.
>
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
Commit message missing , replace "some" in subject with something more
descriptive.
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> ---
> arch/arm/mach-socfpga/in
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> This patch enables SPL build and implementation for Arria 10.
>
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> ---
> arch/arm/Kconfig | 4 ++--
> 1 file chan
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> ---
> arch/arm/mach-socfpga/system_manager.c | 4 ++-
Do NOT EVER patch common code when adding board stuff. Al
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> The drivers is restructured such common functions, gen5 functions, and
> arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
> clock_manager_arria10 respectively.
>
> Signed-off-by: Tien Fong Chee
> Cc:
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> ---
> arch/arm/mach-socfpga/include/mach/pinmux.h | 17 +
> arch/arm/mach-socfpga/pinmux.c | 10
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> Drivers for reset manager is restructured such that common functions,
> gen5 drivers and Arria10 drivers are moved to reset_manager.c,
> reset_manager_gen5.c and reset_manager_arria10.c respectively.
>
> Signed-off-by: Tien
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> The drivers is restructured such common functions, gen5 functions. and
> arria10 functions are moved to misc.c, misc_gen5 and misc_arria10
> respectively.
>
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Ngu
On 01/23/2017 04:51 AM, Dalon Westergreen wrote:
> From: Dalon Westergreen
>
> Move repeated environment settings for socfpga boards
> to a common header.
>
> The default values for the boot partition and the
> OS filesystem partition have changed and as
> as result the default uboot environment
On 01/23/2017 04:51 AM, Dalon Westergreen wrote:
> From: Dalon Westergreen
>
> Remove the default environment as it is now in a common
> header.
>
> Add the CONFIG_DEFAULT_DEVICE_TREE to the board's defconfig
> to set the linux devicetree name.
>
> Signed-off-by: Dalon Westergreen
> ---
> con
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
This needs commit message and Kconfig conversion possibly.
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> ---
> drivers/Makefile | 2 +-
> 1 file changed, 1 inse
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee
>
> This patch adding the Arria10 critical hardware initialization before
> enabling console print out in spl.
>
> Signed-off-by: Tien Fong Chee
> Cc: Marek Vasut
> Cc: Dinh Nguyen
> Cc: Chin Liang See
> Cc: Tien Fong
> --
On 01/23/2017 04:36 AM, Dalon Westergreen wrote:
> Add CycloneV based Terasic DE10 Nano board. The
> board is based on the DE0 Nano but has a larger
> fpga.
>
> Signed-off-by: Dalon Westergreen
Acked-by: Marek Vasut
--
Best regards,
Marek Vasut
___
On Friday 20 January 2017 04:03 AM, Grygorii Strashko wrote:
> Sry
>
> CC:u-boot@lists.denx.de
>
> On 01/19/2017 04:30 PM, Grygorii Strashko wrote:
>> From: Mugunthan V N
>>
>> Add support for programmable MAC impedance configuration and
>> fix typo in DT impedance parameters names.
>>
>> Sign
On 18.1.2017 22:42, Simon Glass wrote:
> Hi Michal,
>
> On 4 January 2017 at 02:40, Michal Simek wrote:
>>
>> Hi,
>>
>> On 3.1.2017 17:15, Moritz Fischer wrote:
>>> Hi Michal,
>>>
>>> On Tue, Jan 3, 2017 at 1:22 AM, Michal Simek
>>> wrote:
On 2.1.2017 20:20, Moritz Fischer wrote:
> Hi
Hi,
On 01/23/2017 08:13 AM, Marcel Ziswiler wrote:
> Hi Samuele
>
> Please note that this list is usually English only.
>
> On Fri, 2017-01-20 at 21:49 +0100, Samuele Bugs wrote:
>> Buoansera in che modo è possibile resettare completamente una emmc e
>> eventualmente di quali modelli samsung sti
This patch provides u-boot support for Liebherr (LWN) mccmon6 board.
Signed-off-by: Lukasz Majewski
---
Changes for v5:
- Remove network configuration data from envs
- Clean up the envs - remove duplicated env variables
Changes for v4:
- Update board/liebherr/mccmon6/MAINTAINERS entry to quiet b
Hi
On 01/20/2017 12:17 AM, Adam Ford wrote:
> On the OMAP36xx/37xx the CONTROL_WKUP_CTRL register has
> a field (bit 6) named GPIO_IO_PWRDNZ. If 0, the IO buffers which
> are related to GPIO_126, 127 and 129 are disabled. Some boards may
> need this for MMC. After the PBIAS is configured, this bi
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