This commit was created as follows:
[1] Rename the option with the following command:
find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e 's/CONFIG_DWMMC/CONFIG_MMC_DW/g'
[2] create the entry for MMC_DW in drivers/mmc/Kconfig
(the prompt and h
CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH is defined in the socfpga_common.h,
but not referenced at all. Remove.
Also, clean-up the README.socfpga. CONFIG_MMC should not be defined
in the header since it was moved to Kconfig by commit c27269953b94
("mmc: complete unfinished move of CONFIG_MMC"). I see no
This CONFIG is not referenced from anywhere.
Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vasut
---
Changes in v2: None
include/configs/da850evm.h | 1 -
include/configs/legoev3.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.
Hi Jaehoon,
2017-01-10 10:41 GMT+09:00 Jaehoon Chung :
> Hi Masahiro,
>
> On 01/10/2017 10:32 AM, Masahiro Yamada wrote:
>> Hi Jaehoon,
>>
>>
>> 2017-01-10 9:55 GMT+09:00 Jaehoon Chung :
>>> Hi Jagan,
>>>
>>> On 01/01/2017 09:11 PM, Masahiro Yamada wrote:
The bare default entry is wrong. Ju
From: Tien Fong Chee
*** BLURB HERE ***
Tien Fong Chee (28):
arm: socfpga: arria10: add additional i2c nodes for Arria10
arm: socfpga: arria10: add sdram defines for Arria10
arm: socfpga: arria10: add board files for the Arria10 SoCDK
arm: socfpga: arria10: add system manager defines
a
From: Tien Fong Chee
Add minimal support for the Arria10 SoCDK.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
board/altera/arria10-socdk/Kconfig | 18 ++
board/altera/arria10-socdk/Makefile
From: Tien Fong Chee
Add the structures for the SDRAM controller on Arria10.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 +
1 file
From: Tien Fong Chee
Add arch_early_init_r function. The Arria10 has a firewall protection
around the SDRAM and OCRAM. These firewalls are to be disabled in order
for U-Boot to function.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang S
From: Tien Fong Chee
Add remaining 3 I2C base addresses for the Arria10.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Reviewed-by: Stefan Roese
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 3 +++
1 f
From: Tien Fong Chee
Add system manager defines for Arria10.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
.../arm/mach-socfpga/include/mach/system_manager.h | 122 +
1 file changed, 122 in
From: Tien Fong Chee
Add a defconfig file for Arria10, which does not include enabling SPL.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Acked-by: Marek Vasut
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
configs/socfpga_arria10_defconfig | 24 +
From: Tien Fong Chee
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/Kconfig | 4 ++--
arch/arm/mach-socfpga/Kconfig | 10 ++
2 files changed, 12 insertions(+), 2 deletions(-)
diff
From: Tien Fong Chee
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 65
From: Tien Fong Chee
Add config for the Arria10 SoC Development Kit.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Acked-by: Marek Vasut
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
include/configs/socfpga_arria10_socdk.h | 94 ++
From: Tien Fong Chee
On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.
Suggested-by: Marek Vasut
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc:
From: Tien Fong Chee
The system manager on Arria10 is not used for pin muxing duties, so wrap
these functions for GEN5 devices only.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/system_m
From: Tien Fong Chee
On the Arria10 device, the bridges are not mapped through the interconnect.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
drivers/fpga/socfpga.c | 2 ++
1 file changed, 2 insertions(+)
di
From: Tien Fong Chee
The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
option in drivers/ddr/altera/Kconfig.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
C
From: Tien Fong Chee
These functions are already in arch/arm/mach-socfpga/board.c
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
board/altera/arria10-socdk/socfpga.c | 17 -
1 file changed, 17 d
From: Tien Fong Chee
There is no dependency on doing a separate clrbits first in the
dwmac_deassert_reset function. Combine them into a single
clrsetbits call.
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arc
From: Tien Fong Chee
Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
From: Tien Fong Chee
On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.
Update the dwmac_deassert_reset function to support both GEN5 and
From: Tien Fong Chee
These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
include/fdtdec.h | 8
l
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10
From: Tien Fong Chee
This patch enables SPL build and implementation for Arria 10.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/
From: Tien Fong Chee
This is initial version of device tree for the Intel socfpga arria10
development kit with sdmmc.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts
From: Tien Fong Chee
Drivers for reset manager is restructured such that common functions,
gen5 drivers and Arria10 drivers are moved to reset_manager.c,
reset_manager_gen5.c and reset_manager_arria10.c respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang
From: Tien Fong Chee
The drivers is restructured such common functions, gen5 functions. and
arria10 functions are moved to misc.c, misc_gen5 and misc_arria10
respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ching Liang See
Cc: Tien Fong
---
arch/arm/mach-socf
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/system_manager.c | 4 ++-
drivers/fpga/socfpga.c | 7 +++--
include/configs/socfpga_arria10_socdk.h | 56
From: Tien Fong Chee
The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ching Liang See
Cc: Tien Fo
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/include/mach/pinmux.h | 17 +
arch/arm/mach-socfpga/pinmux.c | 104
2 files changed, 121 insertions(+)
From: Tien Fong Chee
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
drivers/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/Makefile b/drivers/Makefile
index c19fa14..c15796b 100644
--- a/drivers/Makefi
From: Tien Fong Chee
This patch adding the Arria10 critical hardware initialization before
enabling console print out in spl.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Chin Liang See
Cc: Tien Fong
---
arch/arm/mach-socfpga/spl.c | 79
From: Tien Fong Chee
The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ching Liang See
Cc: Tien Fo
From: Tien Fong Chee
The drivers is restructured such common functions, gen5 functions, and
arria10 functions are moved to clock_manager.c, clock_manager_gen5 and
clock_manager_arria10 respectively.
Signed-off-by: Tien Fong Chee
Cc: Marek Vasut
Cc: Dinh Nguyen
Cc: Ching Liang See
Cc: Tien Fo
Dear Tom,
Could you pull these patches on your master branch?
If there is an issue, let me know, plz.(Buildman was passed.)
The following changes since commit a705ebc81b7f91bbd0ef7c634284208342901149:
Prepare v2017.01 (2017-01-09 11:57:05 -0500)
are available in the git repository at:
http
Hi Masahiro,
On 01/10/2017 01:32 PM, Masahiro Yamada wrote:
> This series is based on commit 3d3a74cc8c.
> Each git-log describes how to re-generate it.
> Buildman test passed.
>
>
> Changes in v2:
> - Re-generate based on v2017.01
>
> Masahiro Yamada (7):
> ARM: socfpga: remove unused CONF
Firmware of Management Complex (MC) should be loaded at 512MB aligned
address. So,
-mc_ram_addr address calculation in mc_get_dram_addr() is updated to
fetch aligned address
-calculate_mc_private_ram_params() is removed as it is no longer required
-num_256mb_blocks calculation is moved to mc_init(
commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor"
breaks u-boot commandline working with long commands
sending to the board.
Since the above patch, you have to setup the fcr register.
For board/archs which enable OF_PLATDATA, the new field
fcr in struct ns16550_platdata is not filled wit
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