Hi Marek, Dinh,
> Are you booting using mainline U-Boot SPL ? :-)
No, we use SPL from U-Boot 2013.
I can quess what you will say now, but it somehow worked before (combination
SPL + U-Boot from 2013).
Is there a way to capture fpga dumps?
I can then compare them to working case.
I can assume t
We can use phys_addr_to for esdhc_base to discard
the #ifdef.
Signed-off-by: Peng Fan
Cc: York Sun
Cc: Yangbo Lu
Cc: Hector Palacios
Cc: Eric Nelson
Cc: Stefano Babic
Cc: Fabio Estevam
Cc: Pantelis Antoniou
Cc: Simon Glass
---
include/fsl_esdhc.h | 6 +-
1 file changed, 1 insertion(+
Support Driver Model for fsl esdhc driver.
In order to minimize the change, reuse the fsl_esdhc_initialize function.
This new way is to fill an fsl_esdhc_cfg struture and pass it
to fsl_esdhc_initialize, just like the code in different board codes.
Introduce a 'struct mmc *mmc' entry in fsl_esdhc
On 03/07/2016 09:18 PM, Daniel Schwierzeck wrote:
> 2016-03-07 14:19 GMT+01:00 Purna Chandra Mandal :
>> MIPS arch implements writes{b,w,l,q}, reads{b,w,l,q}
>> whereas other archs implement __raw version of them.
>> So defining macro writes{bwlq}() to __raw_writes{bwlq}()
>> (and similarly for re
On Wed, Mar 09, 2016 at 05:39:56PM +0530, Lokesh Vutla wrote:
> From: Nishanth Menon
>
> If EMIF is idle for certain amount of DDR cycles, EMIF will put the
> DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register
> is programmed. And also before entering suspend-resume ddr needs
On 03/10/2016 09:58 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
> Hi Marek, Dinh,
Hi,
>> Are you booting using mainline U-Boot SPL ? :-)
>
> No, we use SPL from U-Boot 2013.
> I can quess what you will say now, but it somehow worked before (combination
> SPL + U-Boot from 2013).
I will sa
PIC32 embedded flash banks are memory mapped, directly read by CPU,
and programming (erase followed by write) operation on them are
handled by on-chip NVM controller.
Signed-off-by: Purna Chandra Mandal
---
drivers/mtd/Kconfig | 6 +
drivers/mtd/Makefile | 1 +
drivers/mtd/pic32
Commit 73a1cb27 moved the check whether we should set the architected
timer frequency from CONFIG_SYS_CLK_FREQ to CONFIG_TIMER_CLK_FREQ, but
did not update all users of it.
The one where I (finally) realized why KVM didn't work is the Arndale
board, so this patch adds the respective define to it.
On Thursday 10 March 2016 06:42 PM, Purna Chandra Mandal wrote:
PIC32 embedded flash banks are memory mapped, directly read by CPU,
and programming (erase followed by write) operation on them are
handled by on-chip NVM controller.
Can you please add some more description to understand bit more,
On 03/09/2016 06:25 PM, Marek Vasut wrote:
>
> Thanks for the test!
>
> The speed looks weird, it should be in the 2-3MiB range.
>
> Are you booting using mainline U-Boot SPL ? :-)
>
Yes, I'm using mainline SPL. This Arria5 board is really old so I can't
really say that I have good working H
On 6 March 2016 at 23:51, Chris Zhong wrote:
> The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_REG2,
> and it expects uboot to store the value using a same protocol. But now
> the ddr setting value is different with DMC, so if you enable the DMC,
> system would crash in kernel.
On 8 March 2016 at 11:46, Vagrant Cascadian wrote:
> On 2016-03-05, FUKAUMI Naoki wrote:
>> on v2016.03-rc3, size of SPL image compiled by gcc 5.3.0 is too large for
>> Firefly-RK3288. (it's fine for Rock2)
> ...
>> to reduce size of SPL image, this patch makes configure_emmc() empty for
>> Firefl
On 10 March 2016 at 08:20, Simon Glass wrote:
> On 6 March 2016 at 23:51, Chris Zhong wrote:
>> The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_REG2,
>> and it expects uboot to store the value using a same protocol. But now
>> the ddr setting value is different with DMC, so if
On 17 February 2016 at 12:00, Simon Glass wrote:
> On 17 February 2016 at 00:55, Jeffy Chen wrote:
>>
>> From: Lin Huang
>>
>> emac may use dpll as clock parent, and it request the clock frequency
>> multiples of 50, so change ddr frequency to 400M.
>>
>> Signed-off-by: Lin Huang
>> Signed-off-
Hi Tom,
A few last-minute fixes.
The following changes since commit deff6fb3a7790e93264292982000275e78bb12e5:
malloc: remove !gd handling (2016-03-08 15:01:47 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-rockchip.git
for you to fetch changes up to b5788dc0dd9570
Hello,
Is it possible to use U-boot in order to load FreeRTOS operating system (or
other OS like microCOS), and how ?
Thank you very much for your help
Best Regards
*Mr Bertrand MERCIER*
*Ingénieur-Architecte Logiciel Temps Réel - *
*06 11 73 13 85*
*Real Time Software Architect Engineer*
*+33 6
> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: Thursday, March 10, 2016 3:09 AM
> To: Rajat Srivastava
> Cc: U-Boot Mailing List ; Marek Vašut ;
> Rajesh Bhagat
> Subject: Re: [PATCH] usb: Add new command to regress USB devices
>
During initial DDR training, false parity errors may be detected.
This patch adds workaround to fix the erratum.
Tested on LS2085QDS and LS2080RDB.
Signed-off-by: Shengzhou Liu
---
v2: Integrated York's comments.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
drivers/ddr/fsl/fsl_ddr_
Add support of address parity for DDR4 UDIMM or discrete memory.
It requires to configurate corresponding MR5[2:0] and TIMING_CFG_7[PAR_LAT].
Parity can be turned on/off by hwconfig, e.g. hwconfig=fsl_ddr:parity=on.
Signed-off-by: Shengzhou Liu
---
v2: Integrated York's comments.
doc/README.fsl
On complex USB infrastructures, with many hubs and therefore many
(perhaps unconnected) ports, current U-Boot has a very long USB scanning
time. On my current custom x86 board, this time is over 20 seconds!!!
One of the biggest problems here is a 1 second delay (timeout) in
usb_hub_configure() to c
My current x86 platform (Bay Trail, not in mainline yet) has a quite
complex USB infrastructure with many USB hubs. Here the USB scan takes
an incredible huge amount of time:
starting USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 9 USB Device(s) found
time: 28.415 seconds
This is o
This patch implements an optionally quasi static USB port configuration.
This is done by using an environment variable, that describes the ports
that shall be scanned at the next USB scans (usb start, usb reset).
The "usb_port_use" env variable is used to describe this static USB
configuration. Fo
This patch removes 2 mdelay(200) calls from usb_hub_port_connect_change().
These delays don't seem to be necessary. At least not in my tests. Here
the number for a custom x86 Bay Trail board (not in mainline yet) with
a quite large and complex USB hub infrastructure.
Without this patch:
starting U
Start with a short USB hub reset delay of 10ms. This can be enough for
some configurations.
The 2nd delay at the of the loop is completely removed. Since the delay
hasn't been long enough, a longer delay time of 200ms is assigned. And
will be used in the next loop round.
This hub reset handling i
In a system with a complex USB infrastrcture (many USB hubs), the
power-on delay of mininimum 1 second for each USB hub results in a quite
big USB scanning time. Many USB devices can deal with much lower
power-on delays. In my test system, even 10ms seems to be enough
for the USB device to get dete
Debugging has shown, that all USB hubs are being resetted twice while
USB scanning. This introduces additional delays and makes USB scanning
even more slow. Testing has shown that this 2nd USB hub reset doesn't
seem to be necessary.
This patch now removes this 2nd USB hub reset if CONFIG_USB_FAST_
On Thu, Mar 10, 2016 at 08:41:57AM -0700, Simon Glass wrote:
> Hi Tom,
>
> A few last-minute fixes.
>
> The following changes since commit deff6fb3a7790e93264292982000275e78bb12e5:
>
> malloc: remove !gd handling (2016-03-08 15:01:47 -0500)
>
> are available in the git repository at:
>
>
On Wed, Mar 09, 2016 at 12:01:35PM +0100, Daniel Schwierzeck wrote:
> Hi Tom,
>
> two fixes for MIPS:
> - fix a build error on Travis CI for pic32mzdask board
> - fix cache op for toolchains not supporting __builtin_mips_cache()
>
> please consider pulling, thanks
>
>
> The following changes s
On 03/10/2016 05:18 AM, Alexander Graf wrote:
> Commit 73a1cb27 moved the check whether we should set the architected
> timer frequency from CONFIG_SYS_CLK_FREQ to CONFIG_TIMER_CLK_FREQ, but
> did not update all users of it.
>
> The one where I (finally) realized why KVM didn't work is the Arndale
On 03/10/2016 05:18 AM, Alexander Graf wrote:
> Commit 73a1cb27 moved the check whether we should set the architected
> timer frequency from CONFIG_SYS_CLK_FREQ to CONFIG_TIMER_CLK_FREQ, but
> did not update all users of it.
>
> The one where I (finally) realized why KVM didn't work is the Arndale
From: Stuart Yoder
Remove stream ID partitioning support that has been made
obsolete by upstream device tree bindings that specify how
representing how PCI requester IDs are mapped to MSI specifiers
and SMMU stream IDs.
Signed-off-by: Stuart Yoder
---
-v6: no changes
arch/arm/cpu/armv8/fsl-la
From: Stuart Yoder
A binding for PCI nodes has been finalized specifying how PCI
device IDs can be mapped to MSI specifiers. See
Documentation/devicetree/bindings/pci/pci-msi.txt in the kernel.
For ls2080a and similar Layerscape SoCs, the MSI specifier is the stream
id. A programmable table (L
From: Stuart Yoder
-update comments around how stream IDs are partitioned
-stream IDs allocated to PCI are no longer divided up by
controller, but are instead a contiguous range
Signed-off-by: Stuart Yoder
---
-v6: no changes
.../asm/arch-fsl-layerscape/ls2080a_stream_id.h| 55 +++
From: Stuart Yoder
put pci_get_hose_head() prototype in header so it is available to
external users-- allowing them to find and iterate over all pci controllers
Signed-off-by: Stuart Yoder
---
-v6: no changes
include/pci.h |1 +
1 file changed, 1 insertion(+)
diff --git a/include/pci.h b
From: Stuart Yoder
msi-map properties are used to tell an OS how PCI requester IDs are
mapped to ARM SMMU stream IDs.
for all PCI devices discovered in a system:
-allocate a LUT (look-up-table) entry in that PCI controller
-allocate a stream ID for the device
-program and enable a LUT entr
From: Stuart Yoder
The per-PCI controller LUT (Look-Up-Table) is a 32-entry table
that maps PCI requester IDs (bus/dev/fun) to a stream ID.
Add defines for the register offsets.
Signed-off-by: Stuart Yoder
---
-v6: first version of this patch, just add the LUT #defines
.../include/asm/arch-f
Hi,
> Why are you constantly hung on this FPGA part ? The ethernet is not
> routed through the FPGA, it is connected directly to the HPS. Thus,
> you don't have to care about the FPGA at all, you only care about the
> configuration of the HPS.
Please excuse me for my small experience in this topi
Hi Jagan,
> -Original Message-
> From: jt...@openedev.com [mailto:jt...@openedev.com]
> Sent: Wednesday, March 09, 2016 9:02 PM
> To: Vikas MANOCHA
> Cc: u-boot@lists.denx.de; Albert Aribaud; Antonio Borneo; Heiko Schocher;
> Kamil Lulko; Matt Porter; re...@wp.pl; Scott Wood; Simon Glass;
Just a reminder to apply this patch.
Cheers,
Vikas
> -Original Message-
> From: Vikas MANOCHA
> Sent: Friday, February 05, 2016 10:43 AM
> To: albert.u.b...@aribaud.net; h...@denx.de
> Cc: Vikas MANOCHA; Simon Glass; Stefan Roese; Przemyslaw Marczak;
> re...@wp.pl; open list
> Subject: [P
On Thursday 10 March 2016 11:11 PM, Vikas MANOCHA wrote:
Hi Jagan,
-Original Message-
From: jt...@openedev.com [mailto:jt...@openedev.com]
Sent: Wednesday, March 09, 2016 9:02 PM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; Albert Aribaud; Antonio Borneo; Heiko Schocher;
Kamil Lulko; Mat
Hi,
> -Original Message-
> From: Jagan Teki [mailto:jt...@openedev.com]
> Sent: Thursday, March 10, 2016 9:46 AM
> To: Vikas MANOCHA
> Cc: u-boot@lists.denx.de; Albert Aribaud; Antonio Borneo; Heiko Schocher;
> Kamil Lulko; Matt Porter; re...@wp.pl; Scott Wood; Simon Glass; Stefan
> Roese;
On Thursday 10 March 2016 11:22 PM, Vikas MANOCHA wrote:
Hi,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Thursday, March 10, 2016 9:46 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; Albert Aribaud; Antonio Borneo; Heiko Schocher;
Kamil Lulko; Matt Porter; re...
Hi Jagan,
> -Original Message-
> From: Jagan Teki [mailto:jt...@openedev.com]
> Sent: Thursday, March 10, 2016 9:58 AM
> To: Vikas MANOCHA
> Cc: u-boot@lists.denx.de; Albert Aribaud; Antonio Borneo; Heiko Schocher;
> Kamil Lulko; Matt Porter; re...@wp.pl; Scott Wood; Simon Glass; Stefan
>
On Thursday 10 March 2016 11:47 PM, Vikas MANOCHA wrote:
Hi Jagan,
-Original Message-
From: Jagan Teki [mailto:jt...@openedev.com]
Sent: Thursday, March 10, 2016 9:58 AM
To: Vikas MANOCHA
Cc: u-boot@lists.denx.de; Albert Aribaud; Antonio Borneo; Heiko Schocher;
Kamil Lulko; Matt Porter;
Hi,
On 10-03-16 16:50, Stefan Roese wrote:
Start with a short USB hub reset delay of 10ms. This can be enough for
some configurations.
The 2nd delay at the of the loop is completely removed. Since the delay
hasn't been long enough, a longer delay time of 200ms is assigned. And
will be used in t
On 9 March 2016 at 22:29, york sun wrote:
> On 03/08/2016 07:04 PM, Alison Wang wrote:
>> As QSPI driver is supported in ls1021aqds_sdcard_qspi_defconfig, SPI-NOR
>> with MTD uclass, CONFIG_MTD_DATAFLASH and new flash vendor config
>> CONFIG_SPI_NOR_SPANSION need be enabled.
>>
>> Signed-off-by: A
On 11 March 2016 at 00:23, Jagan Teki wrote:
> On 9 March 2016 at 22:29, york sun wrote:
>> On 03/08/2016 07:04 PM, Alison Wang wrote:
>>> As QSPI driver is supported in ls1021aqds_sdcard_qspi_defconfig, SPI-NOR
>>> with MTD uclass, CONFIG_MTD_DATAFLASH and new flash vendor config
>>> CONFIG_SPI_
Hi,
On 10-03-16 16:50, Stefan Roese wrote:
This patch removes 2 mdelay(200) calls from usb_hub_port_connect_change().
These delays don't seem to be necessary. At least not in my tests. Here
the number for a custom x86 Bay Trail board (not in mainline yet) with
a quite large and complex USB hub i
Hi,
On 10-03-16 16:50, Stefan Roese wrote:
On complex USB infrastructures, with many hubs and therefore many
(perhaps unconnected) ports, current U-Boot has a very long USB scanning
time. On my current custom x86 board, this time is over 20 seconds!!!
One of the biggest problems here is a 1 seco
Hi,
On 10-03-16 16:50, Stefan Roese wrote:
In a system with a complex USB infrastrcture (many USB hubs), the
power-on delay of mininimum 1 second for each USB hub results in a quite
big USB scanning time. Many USB devices can deal with much lower
power-on delays. In my test system, even 10ms see
Hi,
On 10-03-16 16:50, Stefan Roese wrote:
Debugging has shown, that all USB hubs are being resetted twice while
USB scanning. This introduces additional delays and makes USB scanning
even more slow. Testing has shown that this 2nd USB hub reset doesn't
seem to be necessary.
This patch now remo
Hi,
On 10-03-16 16:50, Stefan Roese wrote:
This patch implements an optionally quasi static USB port configuration.
This is done by using an environment variable, that describes the ports
that shall be scanned at the next USB scans (usb start, usb reset).
The "usb_port_use" env variable is used
The Difrnce dit4350 tablet is a tiny tablet with a 4.3" 16:9 480x272 LCD,
A13 SoC, 512M RAM, 4G NAND, solomon systech ssd2532qn6 touchscreen at
i2c1 address 0x48, Memsic MXC622X accelerometer at i2c1 address 0x15 and
rtl8188etv wifi.
The dts file is identical to the one submitted to the upstream k
From: Jiandong Zheng
Add support for the iproc NAND, and enable on Cygnus and NSP boards.
Signed-off-by: Jiandong Zheng
Signed-off-by: Steve Rae
---
There was a previous attempt to implement this "iproc NAND"
(see: http://patchwork.ozlabs.org/patch/505399), however, due to the
amount of change
Configure the NAND device, define partition sizes, and create
the environment space for Cygnus and NSP boards.
Signed-off-by: Steve Rae
---
arch/arm/include/asm/arch-bcmcygnus/configs.h | 33 +++
arch/arm/include/asm/arch-bcmnsp/configs.h| 33
Enable MTD support on Cygnus and NSP boards.
Signed-off-by: Steve Rae
---
arch/arm/include/asm/arch-bcmcygnus/configs.h | 6 ++
arch/arm/include/asm/arch-bcmnsp/configs.h| 6 ++
2 files changed, 12 insertions(+)
diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h
b/arch/arm
- add missing declaration
- update debug output format specifiers
Signed-off-by: Steve Rae
---
the checkpatch warning:
warning: cmd/mtdparts.c,1494: quoted string split across lines
is for the existing code; it is not introduced with this change...
cmd/mtdparts.c | 4 ++--
include/li
... updated the subject line, was:
Re: [U-Boot][PATCH v3 1/3] fastboot: OUT transaction length must be
aligned to wMaxPacketSize
On 15-02-24 02:28 AM, Lukasz Majewski wrote:
Hi Dileep,
OUT transactions must be aligned to wMaxPacketSize for each transfer,
or else transfer will not complete s
On 03/10/2016 08:50 AM, Stefan Roese wrote:
This patch removes 2 mdelay(200) calls from usb_hub_port_connect_change().
These delays don't seem to be necessary. At least not in my tests. Here
the number for a custom x86 Bay Trail board (not in mainline yet) with
a quite large and complex USB hub i
On 03/10/2016 08:50 AM, Stefan Roese wrote:
Start with a short USB hub reset delay of 10ms. This can be enough for
some configurations.
The 2nd delay at the of the loop is completely removed. Since the delay
hasn't been long enough, a longer delay time of 200ms is assigned. And
will be used in t
On 03/10/2016 08:50 AM, Stefan Roese wrote:
Debugging has shown, that all USB hubs are being resetted twice while
USB scanning. This introduces additional delays and makes USB scanning
even more slow. Testing has shown that this 2nd USB hub reset doesn't
seem to be necessary.
This patch now remo
On Thu, Mar 10, 2016 at 3:46 PM, Steve Rae wrote:
> ... updated the subject line, was:
> Re: [U-Boot][PATCH v3 1/3] fastboot: OUT transaction length must be aligned
> to wMaxPacketSize
>
>
>>> -static unsigned int rx_bytes_expected(void)
>>> +static unsigned int rx_bytes_expected(unsigned int ma
The stm_is_locked_sr() function is picked from Linux kernel. For reason
unknown, the 64bit data types used by the function and present in Linux
were replaced with 32bit unsigned ones, which causes trouble.
The testcase performed was done using ST M25P80 chip.
The command used was:
=> sf protect u
On Tue, Mar 1, 2016 at 10:04 AM, Simon Glass wrote:
> On 29 February 2016 at 00:54, Bin Meng wrote:
>> SeaBIOS is an open source implementation of a 16-bit x86 BIOS.
>> It can run in an emulator or natively on x86 hardware with the
>> use of coreboot. With SeaBIOS's help, we can boot some OSes
>>
On Mon, Feb 29, 2016 at 3:54 PM, Bin Meng wrote:
> Now that ACPI is supported on QEMU, enable it.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Simon Glass
> ---
>
> Changes in v2: None
>
> configs/qemu-x86_defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
applied to u-boot-x86/next, thanks!
__
On Mon, Feb 29, 2016 at 3:54 PM, Bin Meng wrote:
> Boting SeaBIOS is done via U-Boot's bootelf command. Document this.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Simon Glass
>
> ---
>
> Changes in v2:
> - Drop patches which were already applied
> - Add more detailed information for testing QEMU/
Hi Simon,
On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
> Commit 1057e6c broke use of the timer with driver model. If the timer is used
> before relocation, then it becomes broken after relocation. This prevents
> some x86 boards from booting. Fix it.
Isn't the broken due to gd not initial
Hi Simon,
On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
> If the device cannot be probed, syscon_get_by_driver_data() will still
> return a useful value in its devp parameter. Ensure that it returns NULL
> instead.
Shouldn't this be the caller's bug, that caller must check the return value
On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
> Some functions do not change the struct gpio_desc parameter. Update these to
> use const so this is clear.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/gpio/gpio-uclass.c | 10 +-
> include/asm-generic/gpio.h | 10 +-
> 2
On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
> Two comments are missing a parameter and there is an extra blank line. Also
> two of the region access macros are misnamed. Correct these problems.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/pci/pci-uclass.c | 1 -
> include/pci.h
On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
> Some CPUs use microcode and each core can have a different version of
> microcode loaded. Also some CPUs support the concept of an integer ID used
> for identification purposes. Add support for these in the CPU uclass.
>
> Signed-off-by: Simon
On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
> It is common to read a config register value, clear and set some bits, then
> write back the updated value. Add functions to do this in one step, for
> convenience.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/pci/pci-uclass.c | 57
> +++
On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
> We can use GPIOs as binary digits for reading 'strapping' values. Each GPIO
> is assigned a single bit and can be set high or low on the circuit board. We
> already have a legacy function for reading these values. Add one that
> supports driver
On 05/03/16 18:08, Anand Moon wrote:
> Enable CONFIG_USB_ETHER_RTL8152 support for Odroid XU4 which
> has support for RTL8153-CG gigabit Ethernet adapter,
> connected over USB 3.0.
>
> commit 9dc8ba19c50fc0b1623c654bcfe6caa903a4c36c added support
> for Realtek 8152/8153 driver.
>
> Signed-off-by:
On Mon, Mar 7, 2016 at 3:37 PM, Anatolij Gustschin wrote:
> Hi Simon,
>
> On Sun, 6 Mar 2016 19:27:48 -0700
> Simon Glass s...@chromium.org wrote:
>
>> At present simple-panel requires regulator support and will not build
>> without it. But some panels do not have a power supply, or at least not
On Fri, Mar 11, 2016 at 11:45 AM, Bin Meng wrote:
> On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
>> Some functions do not change the struct gpio_desc parameter. Update these to
>> use const so this is clear.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> drivers/gpio/gpio-uclass.c | 10 ++
On Fri, Mar 11, 2016 at 11:45 AM, Bin Meng wrote:
> On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
>> Some CPUs use microcode and each core can have a different version of
>> microcode loaded. Also some CPUs support the concept of an integer ID used
>> for identification purposes. Add suppor
On Fri, Mar 11, 2016 at 11:45 AM, Bin Meng wrote:
> On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
>> We can use GPIOs as binary digits for reading 'strapping' values. Each GPIO
>> is assigned a single bit and can be set high or low on the circuit board. We
>> already have a legacy function
On Fri, Mar 11, 2016 at 11:46 AM, Bin Meng wrote:
> On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
>> It is common to read a config register value, clear and set some bits, then
>> write back the updated value. Add functions to do this in one step, for
>> convenience.
>>
>> Signed-off-by: Si
On Fri, Mar 11, 2016 at 11:46 AM, Bin Meng wrote:
> On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
>> Two comments are missing a parameter and there is an extra blank line. Also
>> two of the region access macros are misnamed. Correct these problems.
>>
>> Signed-off-by: Simon Glass
>> ---
Hi Simon,
On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
> Add one more step into the init sequence. This fixes the keyboard on samus,
> which otherwise does not work.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/input/i8042.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --gi
On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
> Output the pointer returned by each call to malloc(). This can be useful
> when debugging memory problems.
>
> Signed-off-by: Simon Glass
> ---
>
> common/malloc_simple.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
Revie
Hi Simon,
On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
> At present on x86 machines with use cache-as-RAM, the memory goes away just
> before board_init_r() is called. This means that serial drivers are
> no-longer unavailable, until initr_dm() it called, etc.
>
> Any attempt to use printf
On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
> This does not need to be modified at run-time, so make it const.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng
___
Hi Simon,
On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
> These two identifiers can be useful for drivers which need to adjust their
> behaviour depending on the CPU family or stepping (revision).
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/cpu.c | 10 ++
> arch/
On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
> This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
> intel_common directory and move it in there.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/Makefile | 1 +
> arch/x86/cpu/intel_com
On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass wrote:
> This is similar to MCH in that it is used in various drivers. Add it to
> the common header.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/ivybridge/bd82x6x.c | 1 +
> arch/x86/cpu/ivybridge/lpc.c | 6 --
> a
Hi Simon,
On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass wrote:
> There are several blocks of registers that are accessed from all over the
> code on Intel CPUs. These don't currently have their own driver and it is
> not clear whether having a driver makes sense.
>
> An example is the Memory Contr
Hi Simon,
On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass wrote:
> This code is used on several Intel CPUs. Move it into a common location.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/intel_common/Makefile | 3 +++
> arch/x86/cpu/intel_common/car.S
Hi Simon,
On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass wrote:
> Some of the LPC code is common to several Intel LPC devices. Move it into a
> common location.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/intel_common/Makefile| 1 +
> arch/x86/cpu/intel_common/lpc_common.c
On Fri, Mar 11, 2016 at 12:18 PM, Bin Meng wrote:
> On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
>> Output the pointer returned by each call to malloc(). This can be useful
>> when debugging memory problems.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> common/malloc_simple.c | 7 +--
On Fri, Mar 11, 2016 at 12:32 PM, Bin Meng wrote:
> On Mon, Mar 7, 2016 at 10:27 AM, Simon Glass wrote:
>> This does not need to be modified at run-time, so make it const.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> arch/x86/cpu/cpu.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>
On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass wrote:
> Many of the model-specific indexes are common to several Intel CPUs. Add
> some more common ones, and remove them from the ivybridge-specific header
> file.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/ivybridge/model_206ax.c
On Fri, Mar 11, 2016 at 1:05 PM, Bin Meng wrote:
> Hi Simon,
>
> On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass wrote:
>> Some of the LPC code is common to several Intel LPC devices. Move it into a
>> common location.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> arch/x86/cpu/intel_common/Makefil
Hi Simon,
On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass wrote:
> Some of the Intel CPU code is common to several Intel CPUs. Move it into a
> common location along with required declarations.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/intel_common/Makefile| 1 +
> arch/x86/c
On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass wrote:
> This same name is used in USB. Add a prefix to distinguish it.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/cpu.c | 4 ++--
> arch/x86/cpu/intel_common/cpu_common.c | 4 ++--
> arch/x86/include/asm/processor.h
Hi Simon,
On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass wrote:
> Some of the Intel ME code is common to several Intel CPUs. Move it into a
> common location. Add a header file for report_platform.c also.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/intel_common/Makefile
On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass wrote:
> This function was removed in the previous clean-up. Drop it from the header
> file also.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/include/asm/arch-ivybridge/sandybridge.h | 2 --
> 1 file changed, 2 deletions(-)
>
Reviewed-by: Bin M
On Fri, Mar 11, 2016 at 1:15 PM, Bin Meng wrote:
> On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass wrote:
>> Many of the model-specific indexes are common to several Intel CPUs. Add
>> some more common ones, and remove them from the ivybridge-specific header
>> file.
>>
>> Signed-off-by: Simon Glass
Hi Simon,
On Mon, Mar 7, 2016 at 10:28 AM, Simon Glass wrote:
> The SATA indexed register write functions are common to several Intel PCHs.
> Move this into a common location.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/intel_common/Makefile| 1 +
> arch/x86/cpu/intel_common/
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