Hi Bin,
On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
> With driver model, board_eth_init() or cpu_eth_init() is not needed.
> Remove the call to these in eth_common_init().
I'm pretty sure Simon needed this when he ported some allwinner board
originally.
3bc427006ac8d0661169ed771b3cac7e86f9
Hi Bin,
On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
> When given a device name string, we should test if it contains "eth"
> before we treat it as an alias.
>
> With this commit, now we are really able to rotate between network
> interfaces with driver model (previously it was broken).
I be
Hi Stefano,
> -Original Message-
> From: Stefano Babic [mailto:sba...@denx.de]
> Sent: Tuesday, August 25, 2015 12:23 PM
> To: Alonso Lazcano Adrian-B38018 ; u-
> b...@lists.denx.de; sba...@denx.de
> Cc: ota...@ossystems.com.br; Estevam Fabio-R49496
> ; Li Frank-B20596 ;
> Garg Nitin-B3717
Hi Bin,
On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
> Move to driver model for USB on Intel Crown Bay.
>
> Signed-off-by: Bin Meng
Reviewed-by: Joe Hershberger
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http://lists.denx.de/mailman/listinfo/u-
Hi Bin,
On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
> Since E1000 driver has been converted to driver model, enable it
> on Intel Crown Bay. But the Intel Topcliff GbE driver has not been
> converted to driver model yet, disable it for now.
If you reorder your series a bit you can squash th
Hi Bin,
On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
> This commit converts pch_gbe ethernet driver to driver model.
>
> Since this driver is only used by Intel Crown Bay board, the
> conversion does not keep the non-dm version.
>
> Signed-off-by: Bin Meng
This looks great.
Acked-by: Joe H
Hi Bin,
On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
> Now that we have converted the pch_gbe driver to driver moel,
> enable it on Intel Crown Bay board.
>
> Signed-off-by: Bin Meng
Looks good if squashed with patch 6.
-Joe
___
U-Boot mailing li
Hi Bin,
(with list this time)
On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
> Add Kconfig option in preparation for moving board to use Kconfig.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/net/Kconfig | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/net/Kconfig b/
Hi Simon,
I'm working on implementing a driver for SD/MMC cards in the framework
GenodeOS. I think you could help me with your experience in this type of
implementation in the u-boot.
The hardware platform on which the driver will work is a ODROID-x2
(exynos4412). I use the DWMMC contoller, but
No need to configure indirect trigger address for every read/write.
Signed-off-by: Vikas Manocha
---
Changes in v4: removed extra type casts.
Changes in v3: added commit message & removed extra bracket.
Changes in v2: Rebased to master
drivers/spi/cadence_qspi_apb.c |9 ++---
1 file ch
This patch is to separate the base trigger from the read/write transfer start
addresses.
Base trigger register address (0x1c register) corresponds to the address which
should be put on AHB bus to handle indirect transfer triggered before.
To handle indirect transfer we need to issue addresses fro
plat->ahbbase renamed to plat->flashbase for better clarity.
Signed-off-by: Vikas Manocha
---
drivers/spi/cadence_qspi.c |8
drivers/spi/cadence_qspi.h |4 ++--
drivers/spi/cadence_qspi_apb.c |4 ++--
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/dri
Fifo width could be different on different socs, e.g. stv0991 & altera soc
have different fifo width.
Signed-off-by: Vikas Manocha
---
Changes in v3: alligned to linux device tree binding.
Changes in v3: none
Changes in v2: Rebased to master
arch/arm/dts/socfpga.dtsi |1 +
arch/arm/dt
This patchset:
- fixes trigger base & transfer start address register programming. This fix
superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb trigger
address setting".
- adds support to get fifo width from device tree
Changes in v4:
- fifo-width & trigger address alligned to l
Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.
Signed-off-by: Vikas Manocha
---
Changes in v4: removed extra type casts.
Changes in v3: none
Changes in v2: Rebased to master
driver
Signed-off-by: Stefan Monnier
---
disk/part_dos.c | 29 +
include/ide.h | 8
2 files changed, 21 insertions(+), 16 deletions(-)
diff --git a/disk/part_dos.c b/disk/part_dos.c
index cf1a36e..adde68a 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -25
No need to configure indirect trigger address for every read/write.
Signed-off-by: Vikas Manocha
---
Changes in v4: fix checkpatch CHECK message.
Changes in v3: added commit message & removed extra bracket.
Changes in v2: Rebased to master
drivers/spi/cadence_qspi_apb.c |9 ++---
1 fil
plat->ahbbase renamed to plat->flashbase for better clarity.
Signed-off-by: Vikas Manocha
---
Changes in v4: new
drivers/spi/cadence_qspi.c |8
drivers/spi/cadence_qspi.h |4 ++--
drivers/spi/cadence_qspi_apb.c |4 ++--
3 files changed, 8 insertions(+), 8 deletions
This patchset:
- fixes trigger base & transfer start address register programming. This fix
superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb trigger
address setting".
- adds support to get fifo width from device tree
Changes in v4:
- fifo-width & trigger address alligned to l
Indirect read/write start addresses are flash start addresses for indirect read
or write transfers. These should be absolute flash addresses instead of
offsets.
Signed-off-by: Vikas Manocha
---
Changes in v4: fixed CHECKPATCH CHECK message.
Changes in v3: none
Changes in v2: Rebased to master
Fifo width could be different on different socs, e.g. stv0991 & altera soc
have different fifo width.
Signed-off-by: Vikas Manocha
---
Changes in v4: alligned to linux device tree binding.
Changes in v3: none
Changes in v2: Rebased to master
arch/arm/dts/socfpga.dtsi |1 +
arch/arm/dt
This patch is to separate the base trigger from the read/write transfer start
addresses.
Base trigger register address (0x1c register) corresponds to the address which
should be put on AHB bus to handle indirect transfer triggered before.
To handle indirect transfer we need to issue addresses fro
Hello,
I need to do some periodic very simple task during u-boot prompt
(while u-boot wais for commands). The task is very simple, just
writing into a watchdog refresh register.
But it seems that it's very difficult to "hack" u-boot with such periodic task.
I see that main loop is waiting in loop
On Tuesday, August 25, 2015 at 09:45:29 PM, Vikas Manocha wrote:
> This patchset:
> - fixes trigger base & transfer start address register programming. This
> fix superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb
> trigger address setting".
> - adds support to get fifo width fr
On 25 August 2015 at 01:22, Bin Meng wrote:
> Move to driver model for USB on Intel Crown Bay.
>
> Signed-off-by: Bin Meng
> ---
>
> configs/crownbay_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Simon Glass
___
U-Boot mailing list
U-
On 25 August 2015 at 01:22, Bin Meng wrote:
> This commit converts pch_gbe ethernet driver to driver model.
>
> Since this driver is only used by Intel Crown Bay board, the
> conversion does not keep the non-dm version.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/net/pch_gbe.c | 133
> +++
On 25 August 2015 at 01:22, Bin Meng wrote:
> Now that we have converted the pch_gbe driver to driver moel,
> enable it on Intel Crown Bay board.
>
> Signed-off-by: Bin Meng
> ---
>
> configs/crownbay_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Simon Glass
_
On Mon, 24 Aug 2015 22:07:16 -0500
Joe Hershberger wrote:
> Hi Lukasz,
>
> On Sun, Aug 23, 2015 at 5:21 PM, Lukasz Majewski
> wrote:
> > This commit series enables DFU subsystem to use ETH and TFTP
> > protocol as a medium for downloading data, which should bring
> > substantial speedup for wri
Add helper macro is_soc_type to identify iMX SoC family
Signed-off-by: Adrian Alonso
---
arch/arm/include/asm/arch-imx/cpu.h | 2 ++
arch/arm/include/asm/arch-mx6/sys_proto.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h
b/arch/arm/include/asm
Add helper macro is_soc_type to identify iMX SoC family
Signed-off-by: Adrian Alonso
---
arch/arm/include/asm/arch-imx/cpu.h | 2 ++
arch/arm/include/asm/arch-mx6/sys_proto.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h
b/arch/arm/include/asm
Rework imx_thermal driver to be used across i.MX
processor that support thermal sensor
Signed-off-by: Adrian Alonso
Signed-off-by: Peng Fan
---
Changes for V2:
Rename read_cpu_temperature to read_cpu_temperature_mx6 use
is_soc_type macro to identify iMX SoC family to call the
correspondind read_
On Thu 2015-08-20 02:18:29, Chin Liang See wrote:
> Enable SDMMC calibration to determine the best setting for
> drvsel and smpsel. It will be triggered whenever there is
> a change of card frequency and bus width. This is to ensure
> reliable transmission between the controller and the card.
>
>
Hi,
On 08/25/2015 01:13 PM, Marek Vasut wrote:
> On Tuesday, August 25, 2015 at 09:45:29 PM, Vikas Manocha wrote:
>> This patchset:
>> - fixes trigger base & transfer start address register programming. This
>> fix superseeds the previous patch "spi: cadence_qspi: Fix the indirect ahb
>> trigger a
On Tue, 2015-07-21 at 16:15 +0800, Peng Fan wrote:
> Check maximum ecc strength for each platfrom to avoid the calculated ecc
> exceed the limitation.
>
> Signed-off-by: Peng Fan
> Signed-off-by: Han Xu
> Reviewed-by: Marek Vasut
> ---
>
> Changes v2:
> Add Marek's reviewed by.
>
> drivers/
Hi Stefano,
> -Original Message-
> From: Stefano Babic [mailto:sba...@denx.de]
> Sent: Sunday, August 23, 2015 11:07 AM
> To: Alonso Lazcano Adrian-B38018 ; u-
> b...@lists.denx.de; sba...@denx.de; Estevam Fabio-R49496
>
> Cc: ota...@ossystems.com.br; Li Frank-B20596 ;
> Garg Nitin-B37173
Add system counter driver for imx7d and mx6ul
imx7 and imx6ul supports system counter timer as well as
GPT timer (arch/arm/imx-common/timer.c); The default for
imx7 is systemcounter timer.
Signed-off-by: Adrian Alonso
Signed-off-by: Ye.Li
---
Changes for V2 to V5: Resend
Changes for V6:
- Update
On 08/25/2015 07:24 AM, Stefan Roese wrote:
> This patch enables the use of the kwboot tool, to boot mainline U-Boot
> on the Marvell Armada XP/38x SoC's. This is done by returning to the
> SoC's BootROM after SPL has initialized the SDRAM. We need to make sure
> to not reconfigure the internal reg
Enable the quad output fast read and quad input fast program
support. Quad mode is supported by Cadence QSPI controller.
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Stefan Roese
Cc: Vikas Manocha
Cc: Jagannadh Teki
Cc: Pavel Machek
Cc: Marek Vasut
---
drivers/spi/cadence_qspi.c |
Hi Joe,
On Wed, Aug 26, 2015 at 3:10 AM, Joe Hershberger
wrote:
> Hi Bin,
>
> (with list this time)
>
> On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
>> Add Kconfig option in preparation for moving board to use Kconfig.
>>
>> Signed-off-by: Bin Meng
>> ---
>>
>> drivers/net/Kconfig | 9
Hi Joe,
On Wed, Aug 26, 2015 at 2:43 AM, Joe Hershberger
wrote:
> Hi Bin,
>
> On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
>> With driver model, board_eth_init() or cpu_eth_init() is not needed.
>> Remove the call to these in eth_common_init().
>
> I'm pretty sure Simon needed this when he p
On 08/21/2015 03:47 AM, Guillaume Gardet wrote:
>
>
> Le 19/08/2015 05:14, Stephen Warren a écrit :
>> On 08/18/2015 08:03 AM, Guillaume GARDET wrote:
>>> Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support to set 'board_rev' and
>>> 'board_name' envs.
>> That states what the patch does rather than
On 08/25/2015 07:10 AM, Guillaume GARDET wrote:
> Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support and enable it to set
> 'board_rev' and 'board_name' envs.
> 'board_rev' can be used in scripts to determine what board we are running on
> and 'board_name' for pretty printing.
The patch itself loo
Hi Scott,
On Tue, Aug 25, 2015 at 04:05:56PM -0500, Scott Wood wrote:
>On Tue, 2015-07-21 at 16:15 +0800, Peng Fan wrote:
>> Check maximum ecc strength for each platfrom to avoid the calculated ecc
>> exceed the limitation.
>>
>> Signed-off-by: Peng Fan
>> Signed-off-by: Han Xu
>> Reviewed-by:
On 08/25/2015 07:46 PM, Ian Lepore wrote:
> On Tue, 2015-08-25 at 19:34 -0600, Stephen Warren wrote:
>> On 08/21/2015 03:47 AM, Guillaume Gardet wrote:
>>>
>>>
>>> Le 19/08/2015 05:14, Stephen Warren a écrit :
On 08/18/2015 08:03 AM, Guillaume GARDET wrote:
> Add CONFIG_ENV_VARS_UBOOT_RUNT
Hi Simon,
On Wed, Aug 26, 2015 at 9:29 AM, Bin Meng wrote:
> Hi Joe,
>
> On Wed, Aug 26, 2015 at 2:43 AM, Joe Hershberger
> wrote:
>> Hi Bin,
>>
>> On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
>>> With driver model, board_eth_init() or cpu_eth_init() is not needed.
>>> Remove the call to th
board_name environment variable was not getting set correctly for Pandaboard A4
and ES
Signed-off-by: David Batzle
CC: Albert Aribaud ; Tom Rini ; Peter
Robinson
---
board/ti/panda/panda.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/ti/panda/panda.c b/board/
On Tue, 2015-08-25 at 19:34 -0600, Stephen Warren wrote:
> On 08/21/2015 03:47 AM, Guillaume Gardet wrote:
> >
> >
> > Le 19/08/2015 05:14, Stephen Warren a écrit :
> >> On 08/18/2015 08:03 AM, Guillaume GARDET wrote:
> >>> Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support to set 'board_rev' and
>
Hi Joe,
On Wed, Aug 26, 2015 at 2:59 AM, Joe Hershberger
wrote:
> Hi Bin,
>
> On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
>> Since E1000 driver has been converted to driver model, enable it
>> on Intel Crown Bay. But the Intel Topcliff GbE driver has not been
>> converted to driver model ye
Hi Bin,
On Tue, Aug 25, 2015 at 8:25 PM, Bin Meng wrote:
> Hi Joe,
>
> On Wed, Aug 26, 2015 at 3:10 AM, Joe Hershberger
> wrote:
>> Hi Bin,
>>
>> (with list this time)
>>
>> On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
>>> Add Kconfig option in preparation for moving board to use Kconfig.
>
Hi Bin,
On Tue, Aug 25, 2015 at 8:29 PM, Bin Meng wrote:
> Hi Joe,
>
> On Wed, Aug 26, 2015 at 2:43 AM, Joe Hershberger
> wrote:
>> Hi Bin,
>>
>> On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
>>> With driver model, board_eth_init() or cpu_eth_init() is not needed.
>>> Remove the call to thes
Hi Masahiro,
On 25 August 2015 at 00:32, Masahiro Yamada
wrote:
> Simon,
>
>
> I've just posted v4.
>
> Sorry for the delay.
>
>
>
> 2015-08-12 23:16 GMT+09:00 Simon Glass :
>> Hi Masahiro,
>>
>> On 10 August 2015 at 10:05, Masahiro Yamada
>> wrote:
>>> This creates a new framework for handling
On 24 August 2015 at 23:51, Masahiro Yamada
wrote:
> This is useful when we want to bind a device, but do not need the
> pointer to the device.
>
> Signed-off-by: Masahiro Yamada
> ---
>
> Changes in v4:
> - Change the subject as suggested by Simon
> - Update the function comments for device_
On 25 August 2015 at 02:53, Misha Komarovskiy wrote:
> If board uses downstream Chrome OS U-Boot as first stage
> bootloader and upstream version is chained second stage,
> 1.1V is minimum voltage borderline.
>
> Signed-off-by: Misha Komarovskiy
> ---
> board/samsung/common/exynos5-dt.c | 7
Hi Nishanth,
On 25 August 2015 at 09:44, Nishanth Menon wrote:
> On 08/25/2015 12:04 AM, Simon Glass wrote:
> [...]
>>> index ..e8fdb124e251
>>> --- /dev/null
>>> +++ b/common/cmd_remoteproc.c
[snip]
>>
>>> + .id = UCLASS_RPROC,
>>> + .name = "remoteproc",
>>> + .fla
+Samsung people
Hi,
On 25 August 2015 at 13:10, Humberto López León wrote:
> Hi Simon,
> I'm working on implementing a driver for SD/MMC cards in the framework
> GenodeOS. I think you could help me with your experience in this type of
> implementation in the u-boot.
> The hardware platform on wh
Hi,
On 25 August 2015 at 19:20, Bin Meng wrote:
> Hi Joe,
>
> On Wed, Aug 26, 2015 at 2:59 AM, Joe Hershberger
> wrote:
>> Hi Bin,
>>
>> On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
>>> Since E1000 driver has been converted to driver model, enable it
>>> on Intel Crown Bay. But the Intel To
On Wed, 2015-08-26 at 08:33 +0800, Peng Fan wrote:
> Hi Scott,
>
> On Tue, Aug 25, 2015 at 04:05:56PM -0500, Scott Wood wrote:
> > On Tue, 2015-07-21 at 16:15 +0800, Peng Fan wrote:
> > > Check maximum ecc strength for each platfrom to avoid the calculated ecc
> > > exceed the limitation.
> > >
>
On Tue, Aug 25, 2015 at 9:28 PM, Simon Glass wrote:
> Hi,
>
> On 25 August 2015 at 19:20, Bin Meng wrote:
>> Hi Joe,
>>
>> On Wed, Aug 26, 2015 at 2:59 AM, Joe Hershberger
>> wrote:
>>> Hi Bin,
>>>
>>> On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
Since E1000 driver has been converted t
Hi Joe,
On Wed, Aug 26, 2015 at 10:24 AM, Joe Hershberger
wrote:
> Hi Bin,
>
> On Tue, Aug 25, 2015 at 8:29 PM, Bin Meng wrote:
>> Hi Joe,
>>
>> On Wed, Aug 26, 2015 at 2:43 AM, Joe Hershberger
>> wrote:
>>> Hi Bin,
>>>
>>> On Tue, Aug 25, 2015 at 2:22 AM, Bin Meng wrote:
With driver mode
Hi Bin,
On Tue, Aug 25, 2015 at 9:36 PM, Bin Meng wrote:
> Hi Joe,
>
> On Wed, Aug 26, 2015 at 10:24 AM, Joe Hershberger
> wrote:
>> Hi Bin,
>>
>> On Tue, Aug 25, 2015 at 8:29 PM, Bin Meng wrote:
>>> Hi Joe,
>>>
>>> On Wed, Aug 26, 2015 at 2:43 AM, Joe Hershberger
>>> wrote:
Hi Bin,
On Tue, Aug 25, 2015 at 09:14:58PM -0500, Scott Wood wrote:
>On Wed, 2015-08-26 at 08:33 +0800, Peng Fan wrote:
>> Hi Scott,
>>
>> On Tue, Aug 25, 2015 at 04:05:56PM -0500, Scott Wood wrote:
>> > On Tue, 2015-07-21 at 16:15 +0800, Peng Fan wrote:
>> > > Check maximum ecc strength for each platfrom
Hi Simon,
2015-08-26 11:26 GMT+09:00 Simon Glass :
>>
>>
+ return -EINVAL;
>>>
>>> That is normally used for an invalid device tree arg. How about -ENOSYS?
>>
>>
>>
>> This is the comment block in U-Boot:
>>
>> #define ENOSYS 38 /* Function not implemented */
>>
Hi,
On 25 August 2015 at 19:36, Bin Meng wrote:
> Hi Joe,
>
> On Wed, Aug 26, 2015 at 10:24 AM, Joe Hershberger
> wrote:
>> Hi Bin,
>>
>> On Tue, Aug 25, 2015 at 8:29 PM, Bin Meng wrote:
>>> Hi Joe,
>>>
>>> On Wed, Aug 26, 2015 at 2:43 AM, Joe Hershberger
>>> wrote:
Hi Bin,
On T
On 24 August 2015 at 22:52, Masahiro Yamada
wrote:
> This driver actually does nothing but test pinctrl uclass, and
> demonstrate how things work.
>
> To try this driver, uncomment /* #define DEBUG */ in the
> drivers/pinctrl/pinctrl-sandbox.c, and debug messages will be
> displayed.
>
> DRAM:
Hi Masahiro,
On 25 August 2015 at 19:42, Masahiro Yamada
wrote:
> Hi Simon,
>
>
>
> 2015-08-26 11:26 GMT+09:00 Simon Glass :
>>>
>>>
> + return -EINVAL;
That is normally used for an invalid device tree arg. How about -ENOSYS?
>>>
>>>
>>>
>>> This is the comment block i
On 24 August 2015 at 22:51, Masahiro Yamada
wrote:
> This creates a new framework for handling of pin control devices,
> i.e. devices that control different aspects of package pins.
>
> This uclass handles pinmuxing and pin configuration; pinmuxing
> controls switching among silicon blocks that sh
At present buildman can compare configurations between commits but the
feature is less useful than it could be. There is no summary by architecture
and changes are not reported on a per-board basis.
Correct these deficiencies so that it is possible to see exactly what is
changing for any number of
Hi Masahiro,
On 17 July 2015 at 05:15, Masahiro Yamada wrote:
> This GPIO controller device is used on UniPhier SoCs.
>
> Signed-off-by: Masahiro Yamada
> ---
>
> Changes in v2:
> - Do not use "ngpio" property to specify the number of GPIO pins.
> Instead, use .data field of OF match table
Hi,
On 17 July 2015 at 05:15, Masahiro Yamada wrote:
> I implemented a GPIO driver based on Driver Model for the UniPhier
> SoC family, but I could not find any good reason why such SoC
> specific GPIO headers are needed.
>
> Signed-off-by: Masahiro Yamada
> ---
>
> Changes in v2: None
>
> arch
On 17 July 2015 at 05:15, Masahiro Yamada wrote:
> Signed-off-by: Masahiro Yamada
> ---
>
> Changes in v2: None
>
> arch/arm/Kconfig | 1 +
> configs/ph1_ld4_defconfig | 1 +
> configs/ph1_pro4_defconfig | 1 +
> configs/ph1_sld8_defconfig | 1 +
> 4 files changed, 4 insertions(+)
Ac
On 17 July 2015 at 05:15, Masahiro Yamada wrote:
> Add GPIO (generic port) controller nodes for PH1-sLD3, PH1-LD4,
> PH1-Pro4 and PH1-sLD8.
>
> Signed-off-by: Masahiro Yamada
> ---
>
> Changes in v2:
> - Drop "ngpio" property
> - Change the compatibility string
>
> arch/arm/dts/uniphier-ph1-
The following changes since commit c851a2458fbc12495f4f786d4eabb612850a5143:
Merge git://git.denx.de/u-boot-socfpga (2015-08-23 20:44:25 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-nand-flash.git
for you to fetch changes up to ecfb8768b16ebf6781ee0df45742674bda8
On 22 August 2015 at 17:28, Simon Glass wrote:
> This requires 'Series-cover_cc' at present which is incorrect. Fix it.
>
> Signed-off-by: Simon Glass
> ---
>
> tools/patman/series.py | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tools/patman/series.py b/tools/patman/s
On 21 August 2015 at 16:27, Simon Glass wrote:
> On 20 August 2015 at 23:44, Bin Meng wrote:
>> Right now PHYS_TO_BUS shows in the Kconfig main menu, move it.
>>
>> Signed-off-by: Bin Meng
>> ---
>>
>> drivers/Kconfig | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Acked-by: Si
On 21 August 2015 at 16:27, Simon Glass wrote:
> On 20 August 2015 at 23:44, Bin Meng wrote:
>> Sort different types of drivers in alphabetical order.
>>
>> Signed-off-by: Bin Meng
>> ---
>>
>> drivers/Kconfig | 50 ++
>> 1 file changed, 26 insert
On 25 August 2015 at 19:26, Simon Glass wrote:
> On 25 August 2015 at 02:53, Misha Komarovskiy wrote:
>> If board uses downstream Chrome OS U-Boot as first stage
>> bootloader and upstream version is chained second stage,
>> 1.1V is minimum voltage borderline.
>>
>> Signed-off-by: Misha Komarovsk
On 21 August 2015 at 16:27, Simon Glass wrote:
> On 20 August 2015 at 23:44, Bin Meng wrote:
>> Make "Generic Driver Options" menu show on the top in the Kconfig.
>>
>> Signed-off-by: Bin Meng
>> ---
>>
>> drivers/Kconfig | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Acked-by
Hi Simon,
2015-08-26 12:53 GMT+09:00 Simon Glass :
> Hi,
>
> On 17 July 2015 at 05:15, Masahiro Yamada
> wrote:
>> I implemented a GPIO driver based on Driver Model for the UniPhier
>> SoC family, but I could not find any good reason why such SoC
>> specific GPIO headers are needed.
>>
>> Signe
2015-08-26 12:53 GMT+09:00 Simon Glass :
> Hi Masahiro,
>
> On 17 July 2015 at 05:15, Masahiro Yamada
> wrote:
>> This GPIO controller device is used on UniPhier SoCs.
>>
>> Signed-off-by: Masahiro Yamada
>> ---
>>
>> Changes in v2:
>> - Do not use "ngpio" property to specify the number of GPI
2015-08-25 0:31 GMT+09:00 Simon Glass :
> +Masahiro
>
>
> On 24 August 2015 at 09:12, Simon Glass wrote:
>> There are a few minor tweaks needed to get this to build. Add them so that
>> the simple pinctrl implementation can be used.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> Changes in v4: Non
Hi Simon,
2015-08-25 0:12 GMT+09:00 Simon Glass :
> My original pinctrl patch operating using a peripheral ID enum. This was
> shared between pinmux and clock and provides an easy way to specify a device
> that needs to be controlled, even it is does not (yet) have a driver within
> driver model
Hi Masahiro,
On 25 August 2015 at 21:30, Masahiro Yamada
wrote:
> Hi Simon,
>
>
>
> 2015-08-25 0:12 GMT+09:00 Simon Glass :
>> My original pinctrl patch operating using a peripheral ID enum. This was
>> shared between pinmux and clock and provides an easy way to specify a device
>> that needs to
Hello Ran,
Am 25.08.2015 um 22:03 schrieb Ran Shalit:
Hello,
I need to do some periodic very simple task during u-boot prompt
(while u-boot wais for commands). The task is very simple, just
writing into a watchdog refresh register.
But it seems that it's very difficult to "hack" u-boot with suc
2015-08-26 13:38 GMT+09:00 Simon Glass :
> Hi Masahiro,
>
> On 25 August 2015 at 21:30, Masahiro Yamada
> wrote:
>> Hi Simon,
>>
>>
>>
>> 2015-08-25 0:12 GMT+09:00 Simon Glass :
>>> My original pinctrl patch operating using a peripheral ID enum. This was
>>> shared between pinmux and clock and pro
Hi,
On 08/25/2015 12:08 PM, Chin Liang See wrote:
> On Tue, 2015-08-25 at 11:36 +0900, Jaehoon Chung wrote:
>> Hi,
>>
>> On 08/25/2015 12:04 AM, Chin Liang See wrote:
>>> On Fri, 2015-08-21 at 14:52 -0600, Simon Glass wrote:
Hi,
On 20 August 2015 at 15:55, Dinh Nguyen wrote:
>
On Tue, 2015-08-25 at 23:01 +0200, ZY - pavel wrote:
> On Thu 2015-08-20 02:18:29, Chin Liang See wrote:
> > Enable SDMMC calibration to determine the best setting for
> > drvsel and smpsel. It will be triggered whenever there is
> > a change of card frequency and bus width. This is to ensure
> > r
On Wed, 2015-08-26 at 14:29 +0900, Jaehoon Chung wrote:
> Hi,
>
> On 08/25/2015 12:08 PM, Chin Liang See wrote:
> > On Tue, 2015-08-25 at 11:36 +0900, Jaehoon Chung wrote:
> >> Hi,
> >>
> >> On 08/25/2015 12:04 AM, Chin Liang See wrote:
> >>> On Fri, 2015-08-21 at 14:52 -0600, Simon Glass wrote:
>
On Wed, Aug 26, 2015 at 7:45 AM, Heiko Schocher wrote:
> Hello Ran,
>
> Am 25.08.2015 um 22:03 schrieb Ran Shalit:
>>
>> Hello,
>>
>> I need to do some periodic very simple task during u-boot prompt
>> (while u-boot wais for commands). The task is very simple, just
>> writing into a watchdog refre
On 08/26/2015 02:47 PM, Chin Liang See wrote:
> On Wed, 2015-08-26 at 14:29 +0900, Jaehoon Chung wrote:
>> Hi,
>>
>> On 08/25/2015 12:08 PM, Chin Liang See wrote:
>>> On Tue, 2015-08-25 at 11:36 +0900, Jaehoon Chung wrote:
Hi,
On 08/25/2015 12:04 AM, Chin Liang See wrote:
> On Fr
On 08/26/2015 11:26 AM, Simon Glass wrote:
> +Samsung people
>
> Hi,
>
> On 25 August 2015 at 13:10, Humberto López León wrote:
>> Hi Simon,
>> I'm working on implementing a driver for SD/MMC cards in the framework
>> GenodeOS. I think you could help me with your experience in this type of
>> im
On Tuesday, August 25, 2015 at 10:56:17 PM, vikas wrote:
> Hi,
>
> On 08/25/2015 01:13 PM, Marek Vasut wrote:
> > On Tuesday, August 25, 2015 at 09:45:29 PM, Vikas Manocha wrote:
> >> This patchset:
> >> - fixes trigger base & transfer start address register programming. This
> >> fix superseeds t
Hi Paul,
thanks for sending this fix.
Basically i can now bring up my board with UART.
Further i want to discuss the whole thing a bit, before we can finish.
On 25.08.2015 17:40, Paul Kocialkowski wrote:
The SYS_BOOT-based fallback shouldn't only check for one of the conditions of
use and the
Hi,
On 08/26/2015 08:23 AM, Jaehoon Chung wrote:
On 08/26/2015 11:26 AM, Simon Glass wrote:
+Samsung people
Hi,
On 25 August 2015 at 13:10, Humberto López León wrote:
Hi Simon,
I'm working on implementing a driver for SD/MMC cards in the framework
GenodeOS. I think you could help me with yo
On Wed, 2015-08-26 at 15:14 +0900, Jaehoon Chung wrote:
> On 08/26/2015 02:47 PM, Chin Liang See wrote:
> > On Wed, 2015-08-26 at 14:29 +0900, Jaehoon Chung wrote:
> >> Hi,
> >>
> >> On 08/25/2015 12:08 PM, Chin Liang See wrote:
> >>> On Tue, 2015-08-25 at 11:36 +0900, Jaehoon Chung wrote:
> H
On Wednesday, August 26, 2015 at 02:09:55 AM, Chin Liang See wrote:
> Enable the quad output fast read and quad input fast program
> support. Quad mode is supported by Cadence QSPI controller.
>
> Signed-off-by: Chin Liang See
> Cc: Dinh Nguyen
> Cc: Stefan Roese
> Cc: Vikas Manocha
> Cc: Jaga
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