On Saturday, August 15, 2015 at 04:15:57 AM, Vikas Manocha wrote:
> No need to configure indirect trigger address for every read/write.
>
> Signed-off-by: Vikas Manocha
> ---
>
> Changes in v3: added commit message & removed extra bracket.
> Changes in v2: Rebased to master
>
> drivers/spi/cad
On Thursday, August 20, 2015 at 07:15:25 AM, Chin Liang See wrote:
> Hi Marek,
Hi,
> On Wed, 2015-08-19 at 03:22 -0500, Chin Liang See wrote:
> > Hi,
> >
> > On Wed, 2015-08-19 at 09:37 +0200, ma...@denx.de wrote:
> > > On Wednesday, August 19, 2015 at 07:55:14 AM, Chin Liang See wrote:
> > > >
On Saturday, August 15, 2015 at 04:15:58 AM, Vikas Manocha wrote:
> Indirect read/write start addresses are flash start addresses for indirect
> read or write transfers. These should be absolute flash addresses instead
> of offsets.
>
> Signed-off-by: Vikas Manocha
> ---
>
> Changes in v3: none
On Saturday, August 15, 2015 at 04:16:00 AM, Vikas Manocha wrote:
> Fifo width could be different on different socs, e.g. stv0991 & altera soc
> have different fifo width.
>
> Signed-off-by: Vikas Manocha
> ---
>
> Changes in v3: none
> Changes in v2: Rebased to master
>
> arch/arm/dts/socfpga
Hi,
On Wed, 2015-08-19 at 14:36 +, ma...@denx.de wrote:
> On Wednesday, August 19, 2015 at 10:21:17 AM, Chin Liang See wrote:
> > Hi,
>
> Hi again,
>
> > On Wed, 2015-08-19 at 02:41 +, ma...@denx.de wrote:
> > > On Wednesday, August 19, 2015 at 07:54:50 AM, Chin Liang See wrote:
> > > >
On Saturday, August 15, 2015 at 04:15:59 AM, Vikas Manocha wrote:
> This patch is to separate the base trigger from the read/write transfer
> start addresses.
>
> Base trigger register address (0x1c register) corresponds to the address
> which should be put on AHB bus to handle indirect transfer t
On 08/19/2015 10:47 PM, Marek Vasut wrote:
> On Wednesday, August 19, 2015 at 10:29:18 PM, Marek Vasut wrote:
>> Repair the maintainer entries so they match the current state of code.
>>
>> Signed-off-by: Marek Vasut
>> ---
>
> Michal, thanks for poking me about this, fixed.
ok then.
Reported-b
On Thursday, August 20, 2015 at 07:28:02 AM, Chin Liang See wrote:
> Hi,
>
> On Wed, 2015-08-19 at 14:36 +, ma...@denx.de wrote:
> > On Wednesday, August 19, 2015 at 10:21:17 AM, Chin Liang See wrote:
> > > Hi,
> >
> > Hi again,
> >
> > > On Wed, 2015-08-19 at 02:41 +, ma...@denx.de wrot
On Thursday 20 August 2015 02:00 AM, Marek Vasut wrote:
> On Wednesday, August 19, 2015 at 10:19:45 AM, Kishon Vijay Abraham I wrote:
>> Changes from v1:
>> Added reviewed-by.
>>
>> This patch series is split from [1] to contain only the usb
>> host/gadget fixes.
>>
>> [1] -> http://permalink.gma
On Thursday, August 20, 2015 at 07:52:18 AM, Kishon Vijay Abraham I wrote:
> On Thursday 20 August 2015 02:00 AM, Marek Vasut wrote:
> > On Wednesday, August 19, 2015 at 10:19:45 AM, Kishon Vijay Abraham I wrote:
> >> Changes from v1:
> >> Added reviewed-by.
> >>
> >> This patch series is split fr
Hi,
On 08/19/2015 03:45 PM, Maxime Ripard wrote:
On Sat, Aug 15, 2015 at 10:02:34PM +0200, Hans de Goede wrote:
CONFIG_SPL_NAND_SUPPORT gets used via IS_ENABLED so it must be defined
to 1, rather then just being defined.
While at remove 2 other unused NAND related defines from sunxi-common.h.
Hi,
On 08/19/2015 03:48 PM, Maxime Ripard wrote:
On Sat, Aug 15, 2015 at 10:02:40PM +0200, Hans de Goede wrote:
Turn off the nand and dma clocks when we're done with the nand, this
puts the nand and dma controllers back into a clean state for when the
kernel boots.
Without this the kernel will
On Thu, 2015-08-20 at 07:27 +0200, ma...@denx.de wrote:
> On Thursday, August 20, 2015 at 07:15:25 AM, Chin Liang See wrote:
> > Hi Marek,
>
> Hi,
>
> > On Wed, 2015-08-19 at 03:22 -0500, Chin Liang See wrote:
> > > Hi,
> > >
> > > On Wed, 2015-08-19 at 09:37 +0200, ma...@denx.de wrote:
> > > >
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