From: Wang Huan
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang
---
Change log:
v6: F
From: Wang Huan
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.
Signed-off-by: Alison Wang
---
Change log:
v6: Use #define instead of magic numbers.
v5: Change the patch order.
v4: Add commit messages.
v3: New file.
board/freesca
From: Wang Huan
The existing i.MX's I2C driver mxc_i2c.c is compatible
with the controller of LS102xA. As I2C's registers
are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to
use 8-bit driver.
This patch is to add I2C 1,2,3 support for LS102xA.
Signed-off-by: Alison Wang
---
Change log:
v6: Fix
From: Wang Huan
On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter
is used. This patch adds the common setting for this
chip.
Signed-off-by: Alison Wang
---
Change log:
v6: No change.
v5: Change the patch order.
v4: Add commit messages.
v3: New file.
board/freescale/common/Makefile
From: Wang Huan
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
From: Alison Wang
Use mb() instead of sync assembly instruction to be
compatible for both ARM and PowerPC.
Signed-off-by: Alison Wang
---
Change log:
v6: Fix checkpatch error.
v5: No change.
v4: No change.
v3: Use mb() to be compatible for both ARM and PowerPC.
Split from the 0004-arm-
From: Wang Huan
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.
Signed-off-by: Alison Wang
---
Change log:
v6: Use #define instead of magic numbers.
v5: Change the patch order.
v4: Add commit messages.
v3: New file.
board/freesca
From: Jingchang Lu
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.
Signed-off-by: Jingchang Lu
Signed-off-by: Yuan Yao
---
Change log:
v6: Fix the influence to other board.
v5: No change.
v4: Ad
From: York Sun
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun
---
Change log:
v6: No change.
v5: No change.
v4: No change.
v3: No change.
v2: No change.
drivers/ddr/fsl/arm_ddr_gen3.c | 2
From: Alison Wang
This patch is to add etsec support for LS102xA. First, Little-endian
descriptor mode should be enabled. So RxBDs and TxBDs are interpreted
with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET
are different from PowerPC, redefine them for LS1021xA.
Signed-off
From: York Sun
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun
---
Change log:
v6: No cha
From: York Sun
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to us
From: Wang Huan
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang
---
Change log:
v6: F
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR
board.
The QorIQ LS1 family is built on Layerscape architecture, the industry's first
software-aware, core-agnostic networking architecture to offer unprecedented
efficiency and scale.
Freescale LS102xA is a set of SoCs
From: Claudiu Manoil
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To
From: Wang Huan
For LS1, esdhc is big-endian IP. Accessing the registers
should be in big-endian mode. So we use esdhc_read32()
to read Host controller capabilities register for LS1.
For LS1, when using CMD12, cmdtype need to be set to
ABORT, otherwise, next read command will hang.
Signed-off-b
From: Wang Huan
For LS102xA, the processor is in little-endian mode, while esdhc IP is
in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE
are added. So accessing ESDHC registers can be determined by ESDHC IP's
endian mode.
Signed-off-by: Alison Wang
---
Change log:
v6: New
From: Wang Huan
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021AQDS board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: York Sun
On 04/09/14 23:42, Masahiro YAMADA wrote:
> Hello Mikyu,
>
>
> Could you pick up this patch, please?
> I think there is a consensus that the maintainership of Arndale board
> should be updated.
>
> Please see
> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/187338
>
>
> 2014-08-04 10:1
From: Claudiu Manoil
Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
workaround for LS1. It has been observed that currently
the Tx stops functioning after a fair amount of Tx traffic
with these settings on. These bits are sticky and once set
they cannot be reset from Linux, for inst
From: Wang Huan
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021ATWR board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Chen Lu
Signed-off-by: Yuan Yao
Signed-off-by: Alison Wang
On 24/07/14 19:42, Przemyslaw Marczak wrote:
> This patch changes MPLL from 800MHz to 880MHz on Odroid.
>
> Signed-off-by: Przemyslaw Marczak
> ---
> board/samsung/odroid/odroid.c | 60
> +--
> 1 file changed, 30 insertions(+), 30 deletions(-)
>
applied
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