> Read-to-read/Write-to-write turnaround for same chip select
> of DDR3 memory, BL/2+2 cycles is enough for these turnarounds.
> Cutting down the turnaround from BL/2+4 to BL/2+2 will improve
> the memory performance.
Please ignore this patch, I will provide one better solution to address
this per
Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and
OTF case, BL/2 cycles is enough for fixed BL8.
Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2
will improve the memory performance.
Signed-off-by: Dave Liu
---
cpu/mp
For 64B cacheline SoC, set the fixed 8-beat burst len,
for 32B cacheline SoC, set the On-The-Fly as default.
Signed-off-by: Dave Liu
---
should go to B2.0.3 release.
cpu/mpc8xxx/ddr/options.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/options.c
Wolfgang Denk wrote:
> I like this approach better than the precious one.
>
> However, I had hoped that we could do without such manual configu-
> ration like CONFIG_FSL_ESDHC_*_ENDIAN. I mean, we already know the
> target byte order, and you know in which byte order you want to
> access the data
Dear Stefano Babic,
In message <4b6a96b3.4060...@denx.de> you wrote:
> Wolfgang Denk wrote:
>
> > I like this approach better than the precious one.
> >
> > However, I had hoped that we could do without such manual configu-
> > ration like CONFIG_FSL_ESDHC_*_ENDIAN. I mean, we already know the
>
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Premi, Sanjeev wrote:
>> -Original Message-
>> From: Premi, Sanjeev
>> Sent: Friday, January 29, 2010 6:44 PM
>> To: u-boot@lists.denx.de
>> Cc: Premi, Sanjeev; Hiremath, Vaibhav
>> Subject: [PATCHv2] OMAP3: Avoid re-write to PRM_CLKSRC_CTRL
>>
>> The function get_osc_clk_speed() is used t
Hi,
I am trying to read SPD data from dimm though I2c.
as the board that i am using it has different I2c register so it is difficult
to match with the register used in u-boot.
Can i get the information about
/*-
| IIC R
Hi,
On Thu, Jan 14, 2010 at 15:00, Anders Darander
wrote:
> From: Anders Darander
>
> Use AT91_GPBR 3 as a bootcount register.
>
As a followup to Werners list of patches not incorporated (from some
time ago), I'd just like to get a comment on the status of this patch.
Should it get reworked s
Hi Ronny,
On Thursday 04 February 2010 15:30:35 Ronny D wrote:
> I am trying to read SPD data from dimm though I2c.
> as the board that i am using it has different I2c register so it is
> difficult to match with the register used in u-boot.
Which platform are you using? PPC4xx? Or something else
Stefano Babic wrote:
> Wolfgang Denk wrote:
>
>> I like this approach better than the precious one.
>>
>> However, I had hoped that we could do without such manual configu-
>> ration like CONFIG_FSL_ESDHC_*_ENDIAN. I mean, we already know the
>> target byte order, and you know in which byte order
Dear Wolfgang,
The problem with AVR32 and the CFI flash driver has a few possible
solutions as noted by Haavard Skinnemoen in the email [1]. The only
thing I can do is to go with the first alternative and set the flash
address as the virtual address which is cache-disabled and works
flawless with
Nimbus Cloud is an AVR32 based single board computer with
256MiB NAND, 64MiB SDRAM, battery backed RTC, LCD/touch
screen support, VGA Output, Ethernet and offers seamless
integration with Indefia's Zigbee transceivers.
---
CREDITS |4 +
MAINTAINERS
On 20.01.2010 18:58, Paulraj, Sandeep wrote:
>
>
>> Subject: Re: [U-Boot] [STATUS] Merge Window closed, waiting for pull
>> requests
>>
>> On 19.01.2010 23:30, Wolfgang Denk wrote:
>>> Hi
>>>
>>> as you probably have noticed, the merge window closed about 24 hours
>>> ago. Checking my list, I still
>
> On 20.01.2010 18:58, Paulraj, Sandeep wrote:
> >
> >
> >> Subject: Re: [U-Boot] [STATUS] Merge Window closed, waiting for pull
> >> requests
> >>
> >> On 19.01.2010 23:30, Wolfgang Denk wrote:
> >>> Hi
> >>>
> >>> as you probably have noticed, the merge window closed about 24 hours
> >>> ago
Hi,
I would like to have all new stuff in the master branch by mid of next
week or so (Feb 10).
To all custodians: please try and pick up any remaining patches
quickly now, and send me pull requests.
To all ARM custodians (and especially Tom): I still see a long list of
unprocessed patches queue
I've been trying to get usbtty working on a DM355 (still isn't
working...) and ran into a bug(?).
In drivers/usb/musb/davinci.h:
struct davinci_usb_regs {
u32 version;
u32 ctrlr;
u32 reserved[0x20];
u32 intclrr;
u32 intmskr;
u32 intmsksetr;
};
Shouldn't this be reserved[0
> -Original Message-
> From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
> On Behalf Of Neal Tew
> Sent: Friday, February 05, 2010 3:33 AM
> To: u-boot@lists.denx.de
> Subject: [U-Boot] TI Davinci and MUSB
>
> I've been trying to get usbtty working on a DM355 (stil
Hi Stefan,
I am using ppc440 for customized board.
U-boot version that i am using is u-boot-2009.11.
Here i am searching for the ppc4xx_i2c structure but not able to get it. on the
other hand i have seen the i2c register macros used in i2c_transfer call.
~Ronny
--- On Thu, 4/2/10, Stefan Roe
[5]? I don't think that's right. Look at the offsets.
-Neal
> I've been trying to get usbtty working on a DM355 (still isn't
> working...) and ran into a bug(?).
>
> In drivers/usb/musb/davinci.h:
>
> struct davinci_usb_regs {
> u32 version;
> u32 ctrlr;
> u32 reserved[0x20];
>
> -Original Message-
> From: Neal Tew [mailto:lo...@mm.st]
> Sent: Friday, February 05, 2010 11:20 AM
> To: u-boot@lists.denx.de
> Cc: Gupta, Ajay Kumar
> Subject: Re: [U-Boot] TI Davinci and MUSB
>
> [5]? I don't think that's right. Look at the offsets.
>
> -Neal
>
> > I've been tryin
Hi Ronny,
On Friday 05 February 2010 06:43:20 Ronny D wrote:
> I am using ppc440 for customized board.
So is this a "normal" AMCC PPC4xx (e.g. 440GX...) or a custom PPC4xx chip? If
it's a common 4xx, then the normal PPC4xx I2C code should just work for you as
well.
> U-boot version that i am
Dear "Gupta, Ajay Kumar",
In message <19f8576c6e063c45be387c64729e7394044a775...@dbde02.ent.ti.com> you
wrote:
>
> > u32 reserved[0x20];
> > u32 intclrr;
> > u32 intmskr;
> > u32 intmsksetr;
> > };
> >
> > Shouldn't this be reserved[0x20/4] ?
>
> Yes, this is a bug. Though the
It is not a normal AMCC PPC4xx, its a customized PPC4xx chip. so I2C code wont
work for me as it is.
i will have to map my register with i2c register used by u-boot.
Now i have downloaded latest u-boot version(Jan 25 2010 12:37 Link
u-boot-latest.tar.bz2 -> u-boot-2009.11.1.tar.bz2) from ftp.
Dear "Gupta, Ajay Kumar",
In message <19f8576c6e063c45be387c64729e7394044a776...@dbde02.ent.ti.com> you
wrote:
>
> Opps, there are actually 32 intermediate register each of 32 bits.
>
> So the correct one is as Neal suggested.
>
> - u32 reserved[0x20];
> + u32 reserved[020/4];
0x20 / 4 = 8
02
> -Original Message-
> From: Wolfgang Denk [mailto:w...@denx.de]
> Sent: Friday, February 05, 2010 12:12 PM
> To: Gupta, Ajay Kumar
> Cc: Neal Tew; u-boot@lists.denx.de
> Subject: Re: [U-Boot] TI Davinci and MUSB
>
> Dear "Gupta, Ajay Kumar",
>
> In message <19f8576c6e063c45be387c64729e
On Friday 05 February 2010 07:41:27 Ronny D wrote:
> It is not a normal AMCC PPC4xx, its a customized PPC4xx chip. so I2C code
> wont work for me as it is.
I see. So you should probably not base your I2C driver code on the PPC4xx
code. Perhaps you could use the soft_i2c code, where you only need
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