Hi Marek,
On 6 April 2017 at 09:33, Marek Vasut wrote:
> On 04/06/2017 04:06 PM, Simon Glass wrote:
>> Hi Marek,
>>
>> On 6 April 2017 at 04:22, Marek Vasut wrote:
>>> On 04/06/2017 04:40 AM, Simon Glass wrote:
Hi Marek,
On 5 April 2017 at 19:32, Marek Vasut wrote:
> On 04/06
On 04/06/2017 04:06 PM, Simon Glass wrote:
> Hi Marek,
>
> On 6 April 2017 at 04:22, Marek Vasut wrote:
>> On 04/06/2017 04:40 AM, Simon Glass wrote:
>>> Hi Marek,
>>>
>>> On 5 April 2017 at 19:32, Marek Vasut wrote:
On 04/06/2017 03:24 AM, Simon Glass wrote:
> Hi Marek,
>
> On
Hi Marek,
On 6 April 2017 at 04:22, Marek Vasut wrote:
> On 04/06/2017 04:40 AM, Simon Glass wrote:
>> Hi Marek,
>>
>> On 5 April 2017 at 19:32, Marek Vasut wrote:
>>> On 04/06/2017 03:24 AM, Simon Glass wrote:
Hi Marek,
On 5 April 2017 at 15:34, Marek Vasut wrote:
> On 04/05
On 04/06/2017 04:40 AM, Simon Glass wrote:
> Hi Marek,
>
> On 5 April 2017 at 19:32, Marek Vasut wrote:
>> On 04/06/2017 03:24 AM, Simon Glass wrote:
>>> Hi Marek,
>>>
>>> On 5 April 2017 at 15:34, Marek Vasut wrote:
On 04/05/2017 05:03 PM, Simon Glass wrote:
> +Tom
>
> Hi Marek
Hi Marek,
On 5 April 2017 at 19:32, Marek Vasut wrote:
> On 04/06/2017 03:24 AM, Simon Glass wrote:
>> Hi Marek,
>>
>> On 5 April 2017 at 15:34, Marek Vasut wrote:
>>> On 04/05/2017 05:03 PM, Simon Glass wrote:
+Tom
Hi Marek,
On 5 April 2017 at 04:21, Marek Vasut wrote:
On 04/06/2017 03:24 AM, Simon Glass wrote:
> Hi Marek,
>
> On 5 April 2017 at 15:34, Marek Vasut wrote:
>> On 04/05/2017 05:03 PM, Simon Glass wrote:
>>> +Tom
>>>
>>> Hi Marek,
>>>
>>> On 5 April 2017 at 04:21, Marek Vasut wrote:
On 04/05/2017 12:08 PM, Simon Glass wrote:
> Hi Marek,
>>
Hi Marek,
On 5 April 2017 at 15:34, Marek Vasut wrote:
> On 04/05/2017 05:03 PM, Simon Glass wrote:
>> +Tom
>>
>> Hi Marek,
>>
>> On 5 April 2017 at 04:21, Marek Vasut wrote:
>>> On 04/05/2017 12:08 PM, Simon Glass wrote:
Hi Marek,
On 5 April 2017 at 03:35, Marek Vasut wrote:
>>>
On 04/05/2017 05:03 PM, Simon Glass wrote:
> +Tom
>
> Hi Marek,
>
> On 5 April 2017 at 04:21, Marek Vasut wrote:
>> On 04/05/2017 12:08 PM, Simon Glass wrote:
>>> Hi Marek,
>>>
>>> On 5 April 2017 at 03:35, Marek Vasut wrote:
On 04/05/2017 04:21 AM, Simon Glass wrote:
> Hi,
>
>
+Tom
Hi Marek,
On 5 April 2017 at 04:21, Marek Vasut wrote:
> On 04/05/2017 12:08 PM, Simon Glass wrote:
>> Hi Marek,
>>
>> On 5 April 2017 at 03:35, Marek Vasut wrote:
>>> On 04/05/2017 04:21 AM, Simon Glass wrote:
Hi,
On 4 April 2017 at 19:26, Kever Yang wrote:
> Hi Eddie,
On 04/05/2017 12:08 PM, Simon Glass wrote:
> Hi Marek,
>
> On 5 April 2017 at 03:35, Marek Vasut wrote:
>> On 04/05/2017 04:21 AM, Simon Glass wrote:
>>> Hi,
>>>
>>> On 4 April 2017 at 19:26, Kever Yang wrote:
Hi Eddie,
We should only need to do only one time cache operat
Hi Marek,
On 5 April 2017 at 03:35, Marek Vasut wrote:
> On 04/05/2017 04:21 AM, Simon Glass wrote:
>> Hi,
>>
>> On 4 April 2017 at 19:26, Kever Yang wrote:
>>> Hi Eddie,
>>>
>>>
>>> We should only need to do only one time cache operation for a buffer
>>>
>>> ready to do DMA transfer, so you
On 04/05/2017 04:21 AM, Simon Glass wrote:
> Hi,
>
> On 4 April 2017 at 19:26, Kever Yang wrote:
>> Hi Eddie,
>>
>>
>> We should only need to do only one time cache operation for a buffer
>>
>> ready to do DMA transfer, so you need to remove another cache invalidate
>>
>> operation for the sa
Hi,
On 4 April 2017 at 19:26, Kever Yang wrote:
> Hi Eddie,
>
>
> We should only need to do only one time cache operation for a buffer
>
> ready to do DMA transfer, so you need to remove another cache invalidate
>
> operation for the same buffer in the same function.
I think this is a more g
Hi Eddie,
We should only need to do only one time cache operation for a buffer
ready to do DMA transfer, so you need to remove another cache invalidate
operation for the same buffer in the same function.
Thanks,
- Kever
On 04/01/2017 02:51 PM, Eddie Cai wrote:
We should invalidate the d
On 04/03/2017 04:43 PM, Brüns, Stefan wrote:
> On Samstag, 1. April 2017 08:51:39 CEST Eddie Cai wrote:
>> We should invalidate the dcache before starting the DMA. In case there are
>> any dirty lines from the DMA buffer in the cache, subsequent cache-line
>> replacements may corrupt the buffer in
On Samstag, 1. April 2017 08:51:39 CEST Eddie Cai wrote:
> We should invalidate the dcache before starting the DMA. In case there are
> any dirty lines from the DMA buffer in the cache, subsequent cache-line
> replacements may corrupt the buffer in memory while the DMA is still going
> on. Cache-li
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