Dear colleagues,
Thank you very much for all the replies.
Finally, I have found the cause of the problem and there is some joy this
weekend.
The problem was the SION bit. The clock has to loop back. I think it is a
u-boot bug in the pinmux table for the imx6dl. The mode ALT2
(ENET_REF_CLK/) for
Thank you for the configuration info about the PHY LAN8720 - I have applied
the changed you have mentioned but I am not getting anywhere.
I have enabled the debug at fec_mxc.c file, and when I execute the 'ping"
command I get the error -22 back, it seems that the problem might be at a
higher layer
Hello Andy,
We use a similar configuration on our custom board. The differences between
your code and ours are :
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
iomux_v3_cfg_t const enet_pad
Thank you for that,
I had a look at mx6slevk and I can't find any major differences. Solo light
is using a fec-light with some extra registers.
Regards,
A
On Thu, Jan 16, 2014 at 11:05 PM, Fabio Estevam wrote:
> On Thu, Jan 16, 2014 at 7:37 PM, Andy Ng wrote:
> > Dear colleagues,
> >
> > I h
On Thu, Jan 16, 2014 at 7:37 PM, Andy Ng wrote:
> Dear colleagues,
>
> I have setup a LAN8720 phy for my imx6Solo/DL custom board but no packets
> coming out.
> I can see 50MHz going into the phy from the REF_OUT Pin of the SOLO, I can
> read the phy ID using the u-boot MDIO commands
> but when I
An update:
I have enabled debug in the u-boot and I get the following error:
fec_send: status 0x8c00 index 0 ret -22
On Thu, Jan 16, 2014 at 9:37 PM, Andy Ng wrote:
> Dear colleagues,
>
> I have setup a LAN8720 phy for my imx6Solo/DL custom board but no packets
> coming out.
> I can see 50MH
6 matches
Mail list logo
