On 11/15/2017 11:38 PM, Rush, Jason A wrote:
> Goldschmidt Simon Wrote:
>> Marek Vasut wrote:
> I don't believe the patchset I submitted for DT bindings were merged in.
I can confirm that. I'd strongly vote for them to get in as cadence_qspi
is otherwise not usable on mach socfpg
Goldschmidt Simon Wrote:
>Marek Vasut wrote:
I don't believe the patchset I submitted for DT bindings were merged in.
>>>
>>> I can confirm that. I'd strongly vote for them to get in as cadence_qspi
>>> is otherwise not usable on mach socfpga.
>>>
>>> How can I ensure a tested-by from me gets
Marek Vasut wrote:
>>> I don't believe the patchset I submitted for DT bindings were merged in.
>>
>> I can confirm that. I'd strongly vote for them to get in as cadence_qspi
>> is otherwise not usable on mach socfpga.
>>
>> How can I ensure a tested-by from me gets related to that patch set?
>> I
On 11/15/2017 05:15 PM, Goldschmidt Simon wrote:
> Rush, Jason A wrote;:
>> I don't believe the patchset I submitted for DT bindings were merged in.
>
> I can confirm that. I'd strongly vote for them to get in as cadence_qspi
> is otherwise not usable on mach socfpga.
>
> How can I ensure a teste
Rush, Jason A wrote;:
> I don't believe the patchset I submitted for DT bindings were merged in.
I can confirm that. I'd strongly vote for them to get in as cadence_qspi
is otherwise not usable on mach socfpga.
How can I ensure a tested-by from me gets related to that patch set?
I can't reply to
Goldschmidt Simon wrote:
> Hi,
>
> I ran into the same issue with the cadence qspi driver and dcache as Jason
> reported (in febuary, I think - I started to monitor U-Boot in july only).
>
> May I ask what's the status here? I do need fixes for this to keep
> mach-socfpga running with qspi. I cur
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