Hi All,
04.07.2012 04:14, Marek Vasut wrote:
Ilya, thank you for saving my back ;-)
And thank you for investing your time into this.
You are welcome ;)
Just posted the patch. No dealing with unaligned buffers from upper
layers for now but at least fatload with aligned address works fine.
Dear Ilya Yanok,
> Hi Tom,
>
> 04.07.2012 00:43, Tom Rini wrote:
> > On 07/03/2012 01:13 PM, Ilya Yanok wrote:
> >> Dear Marek,
> >>
> >> 30.06.2012 23:28, Marek Vasut wrote:
> Not exactly. It never worked (at least on my systems) with D-Cache
> enabled. But at least we had a choice of
Dear Ilya Yanok,
> Dear Marek,
>
> 30.06.2012 23:27, Marek Vasut wrote:
> >>> do {
> >>>
> >>> /* Invalidate dcache */
> >>> invalidate_dcache_range((uint32_t)&qh_list,
> >>>
> >>> (uint32_t)&qh_list +
Dear Tom Rini,
> On 07/03/2012 01:13 PM, Ilya Yanok wrote:
> > Dear Marek,
> >
> > 30.06.2012 23:28, Marek Vasut wrote:
> >>> Not exactly. It never worked (at least on my systems) with D-Cache
> >>> enabled. But at least we had a choice of run-time disabled dcache. With
> >>> the recent changes w
Hi Tom,
04.07.2012 00:43, Tom Rini wrote:
On 07/03/2012 01:13 PM, Ilya Yanok wrote:
Dear Marek,
30.06.2012 23:28, Marek Vasut wrote:
Not exactly. It never worked (at least on my systems) with D-Cache
enabled. But at least we had a choice of run-time disabled dcache. With
the recent changes we
On 07/03/2012 01:13 PM, Ilya Yanok wrote:
> Dear Marek,
>
> 30.06.2012 23:28, Marek Vasut wrote:
>>> Not exactly. It never worked (at least on my systems) with D-Cache
>>> enabled. But at least we had a choice of run-time disabled dcache. With
>>> the recent changes we have to disable cache suppor
Dear Marek,
30.06.2012 23:28, Marek Vasut wrote:
Not exactly. It never worked (at least on my systems) with D-Cache
enabled. But at least we had a choice of run-time disabled dcache. With
the recent changes we have to disable cache support at compile time.
I see what you're after. But do you co
Dear Marek,
30.06.2012 23:27, Marek Vasut wrote:
do {
/* Invalidate dcache */
invalidate_dcache_range((uint32_t)&qh_list,
(uint32_t)&qh_list + sizeof(struct QH));
invalidate_dcache_range((uint32_t)&qh,
Dear Ilya Yanok,
> Dear Marek,
>
> 29.06.2012 04:54, Marek Vasut wrote:
> >> To clarify for everyone, the first part of this series fixes some
> >> alignment issues for things that were not starting address aligned.
> >> There still exist end-address alignment issues within ehci-hcd. The
> >> ti
Dear Ilya Yanok,
> Dear Marek,
>
> 28.06.2012 19:41, Marek Vasut wrote:
> >> Surely. (but that probably was an AM3517 with 64 byte cache line)
> >
> > m28 is imx28 with 32byte cacheline
>
> You are lucky then. But some systems have bigger cacheline, right?
Yes, and I just got a perfect system
Dear Marek,
29.06.2012 04:54, Marek Vasut wrote:
To clarify for everyone, the first part of this series fixes some
alignment issues for things that were not starting address aligned.
There still exist end-address alignment issues within ehci-hcd. The
time I have for this problem right now boils
Dear Marek,
28.06.2012 19:41, Marek Vasut wrote:
Surely. (but that probably was an AM3517 with 64 byte cache line)
m28 is imx28 with 32byte cacheline
You are lucky then. But some systems have bigger cacheline, right?
patch) and loading from ext2 and vfat (worked).
This is just a coincedenc
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On 06/28/2012 05:54 PM, Marek Vasut wrote:
> Dear Tom Rini,
>
>> On 06/28/2012 03:36 PM, Marek Vasut wrote:
>>> Dear Tom Rini,
>>>
On Fri, Jun 29, 2012 at 12:01:58AM +0200, Marek Vasut wrote:
> Dear Tom Rini,
>
>> On 06/28/2012 07:3
Dear Tom Rini,
> On 06/28/2012 03:36 PM, Marek Vasut wrote:
> > Dear Tom Rini,
> >
> >> On Fri, Jun 29, 2012 at 12:01:58AM +0200, Marek Vasut wrote:
> >>> Dear Tom Rini,
> >>>
> On 06/28/2012 07:37 AM, Marek Vasut wrote:
> > Dear Ilya Yanok,
> >
> >> Dear Marek,
> >>
> >>>
On 06/28/2012 03:36 PM, Marek Vasut wrote:
> Dear Tom Rini,
>
>> On Fri, Jun 29, 2012 at 12:01:58AM +0200, Marek Vasut wrote:
>>> Dear Tom Rini,
>>>
On 06/28/2012 07:37 AM, Marek Vasut wrote:
> Dear Ilya Yanok,
>
>> Dear Marek,
>>
>> 28.06.2012 02:48, Marek Vasut wrote:
>>
Dear Tom Rini,
> On Fri, Jun 29, 2012 at 12:01:58AM +0200, Marek Vasut wrote:
> > Dear Tom Rini,
> >
> > > On 06/28/2012 07:37 AM, Marek Vasut wrote:
> > > > Dear Ilya Yanok,
> > > >
> > > >> Dear Marek,
> > > >>
> > > >> 28.06.2012 02:48, Marek Vasut wrote:
> > > Sorry for missing this di
On Fri, Jun 29, 2012 at 12:01:58AM +0200, Marek Vasut wrote:
> Dear Tom Rini,
>
> > On 06/28/2012 07:37 AM, Marek Vasut wrote:
> > > Dear Ilya Yanok,
> > >
> > >> Dear Marek,
> > >>
> > >> 28.06.2012 02:48, Marek Vasut wrote:
> > Sorry for missing this discussion. I think compile-time disab
Dear Tom Rini,
> On 06/28/2012 07:37 AM, Marek Vasut wrote:
> > Dear Ilya Yanok,
> >
> >> Dear Marek,
> >>
> >> 28.06.2012 02:48, Marek Vasut wrote:
> Sorry for missing this discussion. I think compile-time disabling of
> the cache is too brutal.
> ehci-hcd cache handling is broke
On 06/28/2012 07:37 AM, Marek Vasut wrote:
> Dear Ilya Yanok,
>
>> Dear Marek,
>>
>> 28.06.2012 02:48, Marek Vasut wrote:
Sorry for missing this discussion. I think compile-time disabling of the
cache is too brutal.
ehci-hcd cache handling is broken anyway: doing unaligned
flus
Dear Ilya Yanok,
> Dear Marek,
>
> 28.06.2012 18:37, Marek Vasut wrote:
> >> Really? Don't forget my old patch [1] then ;)
> >> Still I think we should rip off all the cache stuff from ehci-hcd until
> >> all patches for upper layers are included. Again, this stuff doesn't do
> >> proper things n
Dear Marek,
28.06.2012 18:37, Marek Vasut wrote:
Really? Don't forget my old patch [1] then ;)
Still I think we should rip off all the cache stuff from ehci-hcd until
all patches for upper layers are included. Again, this stuff doesn't do
proper things now anyway and USB won't work with dcache e
Dear Ilya Yanok,
> Dear Marek,
>
> 28.06.2012 02:48, Marek Vasut wrote:
> >> Sorry for missing this discussion. I think compile-time disabling of the
> >> cache is too brutal.
> >> ehci-hcd cache handling is broken anyway: doing unaligned
> >> flushes/invalidates is a bug, and we know for sure th
Dear Marek,
28.06.2012 02:48, Marek Vasut wrote:
Sorry for missing this discussion. I think compile-time disabling of the
cache is too brutal.
ehci-hcd cache handling is broken anyway: doing unaligned
flushes/invalidates is a bug, and we know for sure that upper layers
don't care about alignment
Hi,
21.06.2012 02:14, Tom Rini wrote:
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Sorry for missing this discussion. I think compile-time disabling of the
cache is too brutal.
ehci-hcd cache handling is broke
Dear Ilya Yanok,
> Hi,
>
> 21.06.2012 02:14, Tom Rini wrote:
> > USB EHCI and DCACHE are not compatible, so disable DCACHE support at
> > build-time as run-time disable is insufficient for USB use.
>
> Sorry for missing this discussion. I think compile-time disabling of the
> cache is too brutal
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