> Hi Marek,
> IMO, Simon has already mentioned the reason of using
> ALLOC_CACHE_ALIGN_BUFFER,
> Please find below my explanation about other doubts.
>
> On Monday 27 February 2012 10:19 PM, Marek Vasut wrote:
> >> As DMA expects the buffers to be equal and larger then
> >> cache lines, This align
Hi Marek,
IMO, Simon has already mentioned the reason of using
ALLOC_CACHE_ALIGN_BUFFER,
Please find below my explanation about other doubts.
On Monday 27 February 2012 10:19 PM, Marek Vasut wrote:
As DMA expects the buffers to be equal and larger then
cache lines, This aligns buffers at cachel
Hi Marek,
On Mon, Feb 27, 2012 at 9:11 AM, Marek Vasut wrote:
>> Hi Marek,
>>
>> On Mon, Feb 27, 2012 at 8:49 AM, Marek Vasut wrote:
>> >> As DMA expects the buffers to be equal and larger then
>> >> cache lines, This aligns buffers at cacheline.
>> >>
>> >> Signed-off-by: Puneet Saxena
>> >> S
> Hi Marek,
>
> On Mon, Feb 27, 2012 at 8:49 AM, Marek Vasut wrote:
> >> As DMA expects the buffers to be equal and larger then
> >> cache lines, This aligns buffers at cacheline.
> >>
> >> Signed-off-by: Puneet Saxena
> >> Signed-off-by: Jim Lin
> >> ---
> >
> > First of all, thanks for this
Hi Marek,
On Mon, Feb 27, 2012 at 8:49 AM, Marek Vasut wrote:
>> As DMA expects the buffers to be equal and larger then
>> cache lines, This aligns buffers at cacheline.
>>
>> Signed-off-by: Puneet Saxena
>> Signed-off-by: Jim Lin
>> ---
>>
>
> First of all, thanks for this patch, it really hel
> As DMA expects the buffers to be equal and larger then
> cache lines, This aligns buffers at cacheline.
>
> Signed-off-by: Puneet Saxena
> Signed-off-by: Jim Lin
> ---
>
First of all, thanks for this patch, it really helps. But, there are a few
things that concern me.
> Changes for V2:
>
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