Hi Stefano,
>> +enum clk_root_index {
>> +MXC_ARM_CLK = 0,
>> +ARM_A53_CLK_ROOT= 0,
>> +ARM_M4_CLK_ROOT = 1,
>> +VPU_A53_CLK_ROOT= 2,
>> +GPU_CORE_CLK_ROOT = 3,
>> +GPU_SHADER_CLK_ROOT
Hi Peng,
On 10/01/2018 06:20, Peng Fan wrote:
> Add clock driver to support i.MX8M.
>
> There are two kind PLLs, FRAC pll and SSCG pll. ROM already
> configured SYS PLL1/2, we only need to configure the output.
> ocotp/i2c/pll decoding and configuration/usdhc/lcdif/dram pll/
> enet clock are conf
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