On 17.01.18 10:26, Amit Tomer wrote:
> Hi,
>
>> + val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
>> + val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio));
>> + val |= (func << BCM2835_GPIO_FSEL_SHIFT(gpio));
>> + writel(val, &gpios->reg->gpf
Hi Alex,
On 16 January 2018 at 05:46, Alexander Graf wrote:
> On the bcm2835 the GPIO IP block is responsible to control pin muxing
> of the configurable pins on the chip.
>
> This adds a simple helper function that allows a device driver to set
> pin muxing according to device tree configuration
Hi,
> + val = readl(&gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
> + val &= ~(BCM2835_GPIO_FSEL_MASK << BCM2835_GPIO_FSEL_SHIFT(gpio));
> + val |= (func << BCM2835_GPIO_FSEL_SHIFT(gpio));
> + writel(val, &gpios->reg->gpfsel[BCM2835_GPIO_FSEL_BANK(gpio)]);
Can clrset
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